Matt Arsenault 2128ba0c85 AMDGPU/GlobalISel: RegBankSelect for carry-in ...

I'm not sure we should be allowing the truncate
to s1 for the inputs. It may be necessary to
create a new VCC reg bank.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350592 91177308-0d34-0410-b5e6-96231b3b80d8

2019-01-08 01:09:09 +00:00

..

AArch64

Reversing the commit in revision 350186. Revision causes regression in 4

2019-01-01 07:28:55 +00:00

AMDGPU

AMDGPU/GlobalISel: RegBankSelect for carry-in

2019-01-08 01:09:09 +00:00

ARC

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ARM

[ARM] ComputeKnownBits to handle extract vectors

2019-01-07 19:01:47 +00:00

AVR

[AVR] Update integration/blink.ll as we now generate sbi/cbi instructions.

2019-01-03 21:25:39 +00:00

BPF

[BPF] Generate BTF DebugInfo under BPF target

2018-12-19 16:40:25 +00:00

Generic

Move llc-start-stop-instance to x86

2018-12-04 18:19:08 +00:00

Hexagon

[DAGCombiner] allow narrowing of add followed by truncate

2018-12-22 17:10:31 +00:00

Inputs

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Lanai

[Targets] Add errors for tiny and kernel codemodel on targets that don't support them

2018-12-07 12:10:23 +00:00

Mips

[MIPS GlobalISel] Select G_SELECT

2018-12-25 14:42:30 +00:00

MIR

[Dwarf/AArch64] Return address signing B key dwarf support

2018-12-21 10:45:08 +00:00

MSP430

[MSP430] Optimize srl/sra in case of A >> (8 + N)

2018-11-19 10:43:02 +00:00

Nios2

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NVPTX

Python compat - print statement

2019-01-03 14:11:33 +00:00

PowerPC

[Power9] Enable the Out-of-Order scheduling model for P9 hw

2019-01-03 05:04:18 +00:00

RISCV

[RISCV] Add support for the various RISC-V FMA instruction variants

2018-12-13 10:49:05 +00:00

SPARC

[Sparc] Use float register for integer constrained with "f" in inline asm

2018-12-13 15:13:29 +00:00

SystemZ

Pythran compat - range vs. xrange

2019-01-03 14:11:58 +00:00

Thumb

[ARM] Complete the Thumb1 shift+and->shift+shift transforms.

2018-12-20 23:39:54 +00:00

Thumb2

[ARM] Enable spilling of the hGPR register class in Thumb2

2018-11-08 13:02:10 +00:00

WebAssembly

[WebAssembly] Optimize Irreducible Control Flow

2019-01-03 23:10:11 +00:00

WinCFGuard

[COFF] Emit @feat.00 on 64-bit and set the CFG bit when emitting guardcf tables

2018-09-19 09:58:30 +00:00

WinEH

[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.

2018-05-09 02:40:45 +00:00

X86

[RegisterCoalescer] dst register's live interval needs to be updated when

2019-01-08 00:26:11 +00:00

XCore

[Targets] Add errors for tiny and kernel codemodel on targets that don't support them

2018-12-07 12:10:23 +00:00