llvm/lib/Target
Evan Cheng 21d5443934 A few more SH{L|R}D peepholes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25473 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-20 01:13:30 +00:00
..
Alpha typo 2006-01-19 21:10:38 +00:00
CBackend yet more C++ standards-compliance stuff. 2005-12-27 10:40:34 +00:00
IA64 fix boolean XOR (which fixes up comparisons..) 2006-01-19 15:18:56 +00:00
PowerPC add a note 2006-01-19 02:09:38 +00:00
Skeleton Support multiple ValueTypes per RegisterClass, needed for upcoming vector 2005-12-01 04:51:06 +00:00
Sparc implement support for f32 arguments past the first 6 words 2006-01-19 07:22:29 +00:00
SparcV8 implement support for f32 arguments past the first 6 words 2006-01-19 07:22:29 +00:00
SparcV9 Support multiple ValueTypes per RegisterClass, needed for upcoming vector 2005-12-01 04:51:06 +00:00
X86 A few more SH{L|R}D peepholes. 2006-01-20 01:13:30 +00:00
Makefile DONT_BUILD_RELINKED is gone and implied by BUILD_ARCHIVE now 2005-10-24 02:26:13 +00:00
MRegisterInfo.cpp Rename MRegisterDesc -> TargetRegisterDesc for consistency 2005-09-30 17:49:27 +00:00
SubtargetFeature.cpp Preparation of supporting scheduling info. Need to find info based on selected 2005-10-25 15:15:28 +00:00
Target.td New DAG node properties SNDPInFlag, SNDPOutFlag, and SNDPOptInFlag to replace 2006-01-09 18:28:21 +00:00
TargetData.cpp Implement a new InvalidateStructLayoutInfo method and add some comments 2006-01-14 00:07:34 +00:00
TargetFrameInfo.cpp
TargetInstrInfo.cpp
TargetMachine.cpp Remove the X86 and PowerPC Simple instruction selectors; their time has 2005-08-18 23:53:15 +00:00
TargetMachineRegistry.cpp 1. Use SubtargetFeatures in llc/lli. 2005-09-01 21:38:21 +00:00
TargetSchedInfo.cpp
TargetSchedule.td add a marker 2005-10-23 22:07:20 +00:00
TargetSelectionDAG.td bswap implementation 2006-01-14 03:14:10 +00:00
TargetSubtarget.cpp