Johnny Chen 22e401f5d4 According to A8.6.16 B (Encoding T3) and A8.3 Conditional execution -- A8.3.1 ...

Pseudocode details of conditional, Condition bits '111x' indicate the
instruction is always executed.  That is, '1111' is a leagl condition field
value, which is now mapped to ARMCC::AL.

Also add a test case for condition field '1111'.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101817 91177308-0d34-0410-b5e6-96231b3b80d8

2010-04-19 21:19:52 +00:00

..

arm-tests.txt

In the same spirit of r101524, which removed the assert() from printAddrMode2OffsetOperand(),

2010-04-16 19:57:21 +00:00

dg.exp

tests: MC/Disassembler tests depend on ARM support being compiler in.

2010-04-15 03:47:20 +00:00

neon-tests.txt

ARM disassembler did not react to recent changes to the NEON instruction table.

2010-04-19 16:20:34 +00:00

simple-tests.txt

testcase for r101538, patch by Nico Schmidt!

2010-04-17 17:22:06 +00:00

thumb-tests.txt

According to A8.6.16 B (Encoding T3) and A8.3 Conditional execution -- A8.3.1

2010-04-19 21:19:52 +00:00