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3c698f35e0
This allows existing DAG combines to work on them, and then we can re-match to BFE if necessary during instruction selection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209462 91177308-0d34-0410-b5e6-96231b3b80d8
427 lines
14 KiB
LLVM
427 lines
14 KiB
LLVM
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood -show-mc-encoding -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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declare i32 @llvm.AMDGPU.bfe.i32(i32, i32, i32) nounwind readnone
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; FUNC-LABEL: @bfe_i32_arg_arg_arg
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; SI: V_BFE_I32
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; EG: BFE_INT
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; EG: encoding: [{{[x0-9a-f]+,[x0-9a-f]+,[x0-9a-f]+,[x0-9a-f]+,[x0-9a-f]+}},0xac
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define void @bfe_i32_arg_arg_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 %src2) nounwind {
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%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 %src0, i32 %src1, i32 %src1) nounwind readnone
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store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @bfe_i32_arg_arg_imm
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; SI: V_BFE_I32
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; EG: BFE_INT
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define void @bfe_i32_arg_arg_imm(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind {
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%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 %src0, i32 %src1, i32 123) nounwind readnone
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store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @bfe_i32_arg_imm_arg
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; SI: V_BFE_I32
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; EG: BFE_INT
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define void @bfe_i32_arg_imm_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src2) nounwind {
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%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 %src0, i32 123, i32 %src2) nounwind readnone
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store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @bfe_i32_imm_arg_arg
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; SI: V_BFE_I32
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; EG: BFE_INT
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define void @bfe_i32_imm_arg_arg(i32 addrspace(1)* %out, i32 %src1, i32 %src2) nounwind {
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%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 123, i32 %src1, i32 %src2) nounwind readnone
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store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @v_bfe_print_arg
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; SI: V_BFE_I32 v{{[0-9]+}}, v{{[0-9]+}}, 2, 8
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define void @v_bfe_print_arg(i32 addrspace(1)* %out, i32 addrspace(1)* %src0) nounwind {
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%load = load i32 addrspace(1)* %src0, align 4
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%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 %load, i32 2, i32 8) nounwind readnone
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store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @bfe_i32_arg_0_width_reg_offset
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; SI-NOT: BFE
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; SI: S_ENDPGM
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; EG-NOT: BFE
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define void @bfe_i32_arg_0_width_reg_offset(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind {
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%bfe_u32 = call i32 @llvm.AMDGPU.bfe.i32(i32 %src0, i32 %src1, i32 0) nounwind readnone
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store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @bfe_i32_arg_0_width_imm_offset
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; SI-NOT: BFE
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; SI: S_ENDPGM
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; EG-NOT: BFE
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define void @bfe_i32_arg_0_width_imm_offset(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind {
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%bfe_u32 = call i32 @llvm.AMDGPU.bfe.i32(i32 %src0, i32 8, i32 0) nounwind readnone
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store i32 %bfe_u32, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @bfe_i32_test_6
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; SI: V_LSHLREV_B32_e32 v{{[0-9]+}}, 31, v{{[0-9]+}}
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; SI: V_ASHRREV_I32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}
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; SI: S_ENDPGM
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define void @bfe_i32_test_6(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%x = load i32 addrspace(1)* %in, align 4
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%shl = shl i32 %x, 31
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%bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %shl, i32 1, i32 31)
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store i32 %bfe, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @bfe_i32_test_7
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; SI-NOT: SHL
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; SI-NOT: BFE
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; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0
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; SI: BUFFER_STORE_DWORD [[VREG]],
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; SI: S_ENDPGM
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define void @bfe_i32_test_7(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%x = load i32 addrspace(1)* %in, align 4
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%shl = shl i32 %x, 31
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%bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %shl, i32 0, i32 31)
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store i32 %bfe, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FIXME: The shifts should be 1 BFE
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; FUNC-LABEL: @bfe_i32_test_8
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; SI: BUFFER_LOAD_DWORD
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; SI: V_BFE_I32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 1
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; SI: S_ENDPGM
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define void @bfe_i32_test_8(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%x = load i32 addrspace(1)* %in, align 4
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%shl = shl i32 %x, 31
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%bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %shl, i32 31, i32 1)
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store i32 %bfe, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @bfe_i32_test_9
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; SI-NOT: BFE
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; SI: V_ASHRREV_I32_e32 v{{[0-9]+}}, 31, v{{[0-9]+}}
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; SI-NOT: BFE
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; SI: S_ENDPGM
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define void @bfe_i32_test_9(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%x = load i32 addrspace(1)* %in, align 4
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%bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %x, i32 31, i32 1)
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store i32 %bfe, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @bfe_i32_test_10
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; SI-NOT: BFE
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; SI: V_ASHRREV_I32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}
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; SI-NOT: BFE
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; SI: S_ENDPGM
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define void @bfe_i32_test_10(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%x = load i32 addrspace(1)* %in, align 4
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%bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %x, i32 1, i32 31)
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store i32 %bfe, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @bfe_i32_test_11
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; SI-NOT: BFE
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; SI: V_ASHRREV_I32_e32 v{{[0-9]+}}, 8, v{{[0-9]+}}
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; SI-NOT: BFE
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; SI: S_ENDPGM
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define void @bfe_i32_test_11(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%x = load i32 addrspace(1)* %in, align 4
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%bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %x, i32 8, i32 24)
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store i32 %bfe, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @bfe_i32_test_12
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; SI-NOT: BFE
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; SI: V_ASHRREV_I32_e32 v{{[0-9]+}}, 24, v{{[0-9]+}}
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; SI-NOT: BFE
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; SI: S_ENDPGM
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define void @bfe_i32_test_12(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%x = load i32 addrspace(1)* %in, align 4
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%bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %x, i32 24, i32 8)
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store i32 %bfe, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @bfe_i32_test_13
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; SI: V_ASHRREV_I32_e32 {{v[0-9]+}}, 31, {{v[0-9]+}}
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; SI-NOT: BFE
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; SI: S_ENDPGM
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define void @bfe_i32_test_13(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%x = load i32 addrspace(1)* %in, align 4
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%shl = ashr i32 %x, 31
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%bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %shl, i32 31, i32 1)
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store i32 %bfe, i32 addrspace(1)* %out, align 4 ret void
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}
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; FUNC-LABEL: @bfe_i32_test_14
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; SI-NOT: LSHR
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; SI-NOT: BFE
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; SI: S_ENDPGM
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define void @bfe_i32_test_14(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%x = load i32 addrspace(1)* %in, align 4
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%shl = lshr i32 %x, 31
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%bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %shl, i32 31, i32 1)
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store i32 %bfe, i32 addrspace(1)* %out, align 4 ret void
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}
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; FUNC-LABEL: @bfe_i32_constant_fold_test_0
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; SI-NOT: BFE
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; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0
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; SI: BUFFER_STORE_DWORD [[VREG]],
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; SI: S_ENDPGM
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; EG-NOT: BFE
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define void @bfe_i32_constant_fold_test_0(i32 addrspace(1)* %out) nounwind {
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%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 0, i32 0, i32 0) nounwind readnone
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store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @bfe_i32_constant_fold_test_1
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; SI-NOT: BFE
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; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0
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; SI: BUFFER_STORE_DWORD [[VREG]],
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; SI: S_ENDPGM
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; EG-NOT: BFE
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define void @bfe_i32_constant_fold_test_1(i32 addrspace(1)* %out) nounwind {
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%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 12334, i32 0, i32 0) nounwind readnone
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store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @bfe_i32_constant_fold_test_2
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; SI-NOT: BFE
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; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0
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; SI: BUFFER_STORE_DWORD [[VREG]],
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; SI: S_ENDPGM
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; EG-NOT: BFE
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define void @bfe_i32_constant_fold_test_2(i32 addrspace(1)* %out) nounwind {
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%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 0, i32 0, i32 1) nounwind readnone
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store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @bfe_i32_constant_fold_test_3
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; SI-NOT: BFE
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; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], -1
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; SI: BUFFER_STORE_DWORD [[VREG]],
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; SI: S_ENDPGM
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; EG-NOT: BFE
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define void @bfe_i32_constant_fold_test_3(i32 addrspace(1)* %out) nounwind {
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%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 1, i32 0, i32 1) nounwind readnone
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store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @bfe_i32_constant_fold_test_4
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; SI-NOT: BFE
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; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], -1
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; SI: BUFFER_STORE_DWORD [[VREG]],
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; SI: S_ENDPGM
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; EG-NOT: BFE
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define void @bfe_i32_constant_fold_test_4(i32 addrspace(1)* %out) nounwind {
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%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 4294967295, i32 0, i32 1) nounwind readnone
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store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @bfe_i32_constant_fold_test_5
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; SI-NOT: BFE
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; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], -1
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; SI: BUFFER_STORE_DWORD [[VREG]],
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; SI: S_ENDPGM
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; EG-NOT: BFE
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define void @bfe_i32_constant_fold_test_5(i32 addrspace(1)* %out) nounwind {
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%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 128, i32 7, i32 1) nounwind readnone
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store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @bfe_i32_constant_fold_test_6
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; SI-NOT: BFE
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; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0xffffff80
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; SI: BUFFER_STORE_DWORD [[VREG]],
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; SI: S_ENDPGM
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; EG-NOT: BFE
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define void @bfe_i32_constant_fold_test_6(i32 addrspace(1)* %out) nounwind {
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%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 128, i32 0, i32 8) nounwind readnone
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store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @bfe_i32_constant_fold_test_7
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; SI-NOT: BFE
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; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0x7f
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; SI: BUFFER_STORE_DWORD [[VREG]],
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; SI: S_ENDPGM
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; EG-NOT: BFE
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define void @bfe_i32_constant_fold_test_7(i32 addrspace(1)* %out) nounwind {
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%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 127, i32 0, i32 8) nounwind readnone
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store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @bfe_i32_constant_fold_test_8
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; SI-NOT: BFE
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; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 1
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; SI: BUFFER_STORE_DWORD [[VREG]],
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; SI: S_ENDPGM
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; EG-NOT: BFE
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define void @bfe_i32_constant_fold_test_8(i32 addrspace(1)* %out) nounwind {
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%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 127, i32 6, i32 8) nounwind readnone
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store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @bfe_i32_constant_fold_test_9
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; SI-NOT: BFE
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; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 1
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; SI: BUFFER_STORE_DWORD [[VREG]],
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; SI: S_ENDPGM
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; EG-NOT: BFE
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define void @bfe_i32_constant_fold_test_9(i32 addrspace(1)* %out) nounwind {
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%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 65536, i32 16, i32 8) nounwind readnone
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store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @bfe_i32_constant_fold_test_10
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; SI-NOT: BFE
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; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0
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; SI: BUFFER_STORE_DWORD [[VREG]],
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; SI: S_ENDPGM
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; EG-NOT: BFE
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define void @bfe_i32_constant_fold_test_10(i32 addrspace(1)* %out) nounwind {
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%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 65535, i32 16, i32 16) nounwind readnone
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store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @bfe_i32_constant_fold_test_11
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; SI-NOT: BFE
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; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], -6
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; SI: BUFFER_STORE_DWORD [[VREG]],
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; SI: S_ENDPGM
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; EG-NOT: BFE
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define void @bfe_i32_constant_fold_test_11(i32 addrspace(1)* %out) nounwind {
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%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 160, i32 4, i32 4) nounwind readnone
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store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @bfe_i32_constant_fold_test_12
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; SI-NOT: BFE
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; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0
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; SI: BUFFER_STORE_DWORD [[VREG]],
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; SI: S_ENDPGM
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; EG-NOT: BFE
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define void @bfe_i32_constant_fold_test_12(i32 addrspace(1)* %out) nounwind {
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%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 160, i32 31, i32 1) nounwind readnone
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store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @bfe_i32_constant_fold_test_13
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; SI-NOT: BFE
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; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 1
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; SI: BUFFER_STORE_DWORD [[VREG]],
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; SI: S_ENDPGM
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; EG-NOT: BFE
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define void @bfe_i32_constant_fold_test_13(i32 addrspace(1)* %out) nounwind {
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%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 131070, i32 16, i32 16) nounwind readnone
|
|
store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: @bfe_i32_constant_fold_test_14
|
|
; SI-NOT: BFE
|
|
; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 40
|
|
; SI: BUFFER_STORE_DWORD [[VREG]],
|
|
; SI: S_ENDPGM
|
|
; EG-NOT: BFE
|
|
define void @bfe_i32_constant_fold_test_14(i32 addrspace(1)* %out) nounwind {
|
|
%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 160, i32 2, i32 30) nounwind readnone
|
|
store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: @bfe_i32_constant_fold_test_15
|
|
; SI-NOT: BFE
|
|
; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 10
|
|
; SI: BUFFER_STORE_DWORD [[VREG]],
|
|
; SI: S_ENDPGM
|
|
; EG-NOT: BFE
|
|
define void @bfe_i32_constant_fold_test_15(i32 addrspace(1)* %out) nounwind {
|
|
%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 160, i32 4, i32 28) nounwind readnone
|
|
store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: @bfe_i32_constant_fold_test_16
|
|
; SI-NOT: BFE
|
|
; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], -1
|
|
; SI: BUFFER_STORE_DWORD [[VREG]],
|
|
; SI: S_ENDPGM
|
|
; EG-NOT: BFE
|
|
define void @bfe_i32_constant_fold_test_16(i32 addrspace(1)* %out) nounwind {
|
|
%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 4294967295, i32 1, i32 7) nounwind readnone
|
|
store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: @bfe_i32_constant_fold_test_17
|
|
; SI-NOT: BFE
|
|
; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0x7f
|
|
; SI: BUFFER_STORE_DWORD [[VREG]],
|
|
; SI: S_ENDPGM
|
|
; EG-NOT: BFE
|
|
define void @bfe_i32_constant_fold_test_17(i32 addrspace(1)* %out) nounwind {
|
|
%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 255, i32 1, i32 31) nounwind readnone
|
|
store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: @bfe_i32_constant_fold_test_18
|
|
; SI-NOT: BFE
|
|
; SI: V_MOV_B32_e32 [[VREG:v[0-9]+]], 0
|
|
; SI: BUFFER_STORE_DWORD [[VREG]],
|
|
; SI: S_ENDPGM
|
|
; EG-NOT: BFE
|
|
define void @bfe_i32_constant_fold_test_18(i32 addrspace(1)* %out) nounwind {
|
|
%bfe_i32 = call i32 @llvm.AMDGPU.bfe.i32(i32 255, i32 31, i32 1) nounwind readnone
|
|
store i32 %bfe_i32, i32 addrspace(1)* %out, align 4
|
|
ret void
|
|
}
|
|
|
|
; XXX - This should really be a single BFE, but the sext_inreg of the
|
|
; extended type i24 is never custom lowered.
|
|
; FUNC-LABEL: @bfe_sext_in_reg_i24
|
|
; SI: BUFFER_LOAD_DWORD [[LOAD:v[0-9]+]],
|
|
; SI: V_LSHLREV_B32_e32 {{v[0-9]+}}, 8, {{v[0-9]+}}
|
|
; SI: V_ASHRREV_I32_e32 {{v[0-9]+}}, 8, {{v[0-9]+}}
|
|
; XSI: V_BFE_I32 [[BFE:v[0-9]+]], [[LOAD]], 0, 8
|
|
; XSI-NOT: SHL
|
|
; XSI-NOT: SHR
|
|
; XSI: BUFFER_STORE_DWORD [[BFE]],
|
|
define void @bfe_sext_in_reg_i24(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
|
|
%x = load i32 addrspace(1)* %in, align 4
|
|
%bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %x, i32 0, i32 24)
|
|
%shl = shl i32 %bfe, 8
|
|
%ashr = ashr i32 %shl, 8
|
|
store i32 %ashr, i32 addrspace(1)* %out, align 4
|
|
ret void
|
|
}
|