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https://github.com/RPCS3/llvm.git
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Matt Arsenault
9f7e91552b
The operand types were defined to fit the fp16_to_fp node, which has the half as an integer type. v_cvt_f32_f16 does support source modifiers, so change this to have an FP type and modifiers. For targets without legal f16, this requires recognizing the bit operations and trying to produce them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293857 91177308-0d34-0410-b5e6-96231b3b80d8
95 lines
3.5 KiB
LLVM
95 lines
3.5 KiB
LLVM
; RUN: llc -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s
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; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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; DAGCombiner will transform:
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; (fabs (f16 bitcast (i16 a))) => (f16 bitcast (and (i16 a), 0x7FFFFFFF))
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; unless isFabsFree returns true
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; GCN-LABEL: {{^}}fabs_free_f16:
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; GCN: flat_load_ushort [[VAL:v[0-9]+]],
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; GCN: v_and_b32_e32 [[RESULT:v[0-9]+]], 0x7fff, [[VAL]]
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; GCN: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define void @fabs_free_f16(half addrspace(1)* %out, i16 %in) {
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%bc= bitcast i16 %in to half
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%fabs = call half @llvm.fabs.f16(half %bc)
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store half %fabs, half addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}fabs_f16:
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; CI: flat_load_ushort [[VAL:v[0-9]+]],
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; CI: v_and_b32_e32 [[CVT0:v[0-9]+]], 0x7fff, [[VAL]]
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; CI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define void @fabs_f16(half addrspace(1)* %out, half %in) {
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%fabs = call half @llvm.fabs.f16(half %in)
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store half %fabs, half addrspace(1)* %out
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ret void
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}
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; FIXME: Should be able to use single and
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; GCN-LABEL: {{^}}fabs_v2f16:
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; CI: s_movk_i32 [[MASK:s[0-9]+]], 0x7fff
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; CI: v_and_b32_e32 v{{[0-9]+}}, [[MASK]], v{{[0-9]+}}
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; CI: v_and_b32_e32 v{{[0-9]+}}, [[MASK]], v{{[0-9]+}}
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; VI: flat_load_ushort [[LO:v[0-9]+]]
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; VI: flat_load_ushort [[HI:v[0-9]+]]
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; VI: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x7fff{{$}}
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; VI-DAG: v_and_b32_e32 [[FABS_LO:v[0-9]+]], [[MASK]], [[LO]]
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; VI-DAG: v_and_b32_e32 [[FABS_LO:v[0-9]+]], [[MASK]], [[HI]]
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; VI-DAG: v_lshlrev_b32_e32 v{{[0-9]+}}, 16,
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; VI-DAG: v_and_b32_e32 v{{[0-9]+}}, 0xffff,
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; VI: v_or_b32
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; VI: flat_store_dword
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define void @fabs_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %in) {
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%fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %in)
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store <2 x half> %fabs, <2 x half> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}fabs_v4f16:
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; CI: s_movk_i32 [[MASK:s[0-9]+]], 0x7fff
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; CI: v_and_b32_e32 v{{[0-9]+}}, [[MASK]], v{{[0-9]+}}
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; CI: v_and_b32_e32 v{{[0-9]+}}, [[MASK]], v{{[0-9]+}}
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; CI: v_and_b32_e32 v{{[0-9]+}}, [[MASK]], v{{[0-9]+}}
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; CI: v_and_b32_e32 v{{[0-9]+}}, [[MASK]], v{{[0-9]+}}
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; VI: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x7fff{{$}}
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; VI: v_and_b32_e32 v{{[0-9]+}}, [[MASK]], v{{[0-9]+}}
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; VI: v_and_b32_e32 v{{[0-9]+}}, [[MASK]], v{{[0-9]+}}
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; VI: v_and_b32_e32 v{{[0-9]+}}, [[MASK]], v{{[0-9]+}}
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; VI: v_and_b32_e32 v{{[0-9]+}}, [[MASK]], v{{[0-9]+}}
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; GCN: flat_store_dwordx2
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define void @fabs_v4f16(<4 x half> addrspace(1)* %out, <4 x half> %in) {
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%fabs = call <4 x half> @llvm.fabs.v4f16(<4 x half> %in)
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store <4 x half> %fabs, <4 x half> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}fabs_fold_f16:
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; GCN: flat_load_ushort [[IN0:v[0-9]+]]
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; GCN: flat_load_ushort [[IN1:v[0-9]+]]
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; CI-DAG: v_cvt_f32_f16_e32 [[CVT0:v[0-9]+]], [[IN0]]
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; CI-DAG: v_cvt_f32_f16_e64 [[ABS_CVT1:v[0-9]+]], |[[IN1]]|
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; CI: v_mul_f32_e32 [[RESULT:v[0-9]+]], [[CVT0]], [[ABS_CVT1]]
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; CI: v_cvt_f16_f32_e32 [[CVTRESULT:v[0-9]+]], [[RESULT]]
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; CI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[CVTRESULT]]
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; VI-NOT: and
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; VI: v_mul_f16_e64 [[RESULT:v[0-9]+]], |[[IN1]]|, [[IN0]]
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; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define void @fabs_fold_f16(half addrspace(1)* %out, half %in0, half %in1) {
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%fabs = call half @llvm.fabs.f16(half %in0)
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%fmul = fmul half %fabs, %in1
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store half %fmul, half addrspace(1)* %out
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ret void
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}
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declare half @llvm.fabs.f16(half) readnone
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declare <2 x half> @llvm.fabs.v2f16(<2 x half>) readnone
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declare <4 x half> @llvm.fabs.v4f16(<4 x half>) readnone
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