Bill Schmidt 26160f4e64 When generating spill and reload code for vector registers on PowerPC, ... the compiler makes use of GPR0. However, there are two flavors of GPR0 defined by the target: the 32-bit GPR0 (R0) and the 64-bit GPR0 (X0). The spill/reload code makes use of R0 regardless of whether we are generating 32- or 64-bit code. This patch corrects the problem in the obvious manner, using X0 and ADDI8 for 64-bit and R0 and ADDI for 32-bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165658 91177308-0d34-0410-b5e6-96231b3b80d8		2012-10-10 21:25:01 +00:00
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ARM	Fix for LDRB instruction:	2012-10-10 11:43:40 +00:00
CellSPU	Fix broken tests.	2012-10-02 15:49:34 +00:00
CPP	test commit	2012-07-18 17:53:05 +00:00
Generic	BranchProb: modify the definition of an edge in BranchProbabilityInfo to handle	2012-08-24 18:14:27 +00:00
Hexagon	LLVM Bug Fix 13709: Remove needless lsr(Rp, #32) instruction access the	2012-09-05 16:01:40 +00:00
MBlaze	Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu	2012-03-25 09:02:19 +00:00
Mips	Implement MipsTargetLowering::CanLowerReturn.	2012-10-10 01:27:09 +00:00
MSP430	Reapply r161633-161634 "Partition use lists so defs always come before uses.""	2012-08-10 00:21:30 +00:00
NVPTX	Add llvm.fabs intrinsic.	2012-05-28 21:48:37 +00:00
PowerPC	When generating spill and reload code for vector registers on PowerPC,	2012-10-10 21:25:01 +00:00
SPARC	Fix broken tests.	2012-10-02 15:49:34 +00:00
Thumb	Fix Thumb2 fixup kind in the integrated-as.	2012-09-01 15:06:36 +00:00
Thumb2	Add LLVM support for Swift.	2012-09-29 21:43:49 +00:00
X86	Specify CPU model to avoid breaking ATOM builds	2012-10-10 18:04:52 +00:00
XCore	Fix pattern for MKMSK instruction.	2012-06-13 17:59:12 +00:00