Craig Topper 267a504434 [X86][ARM][TargetLowering] Add SrcVT to isExtractSubvectorCheap ... Summary: Without the SrcVT its hard to know what is really being asked for. For example if your target has 128, 256, and 512 bit vectors. Maybe extracting 128 from 256 is cheap, but maybe extracting 128 from 512 is not. For x86 we do support extracting a quarter of a 512-bit register. But for i1 vectors we don't have isel patterns for extracting arbitrary pieces. So we need this to have a correct implementation of isExtractSubvectorCheap for mask vectors. Reviewers: RKSimon, zvi, efriedma Reviewed By: RKSimon Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D36649 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310793 91177308-0d34-0410-b5e6-96231b3b80d8		2017-08-13 17:29:07 +00:00
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llvm	[X86][ARM][TargetLowering] Add SrcVT to isExtractSubvectorCheap	2017-08-13 17:29:07 +00:00
llvm-c	[ORC] Errorize the ORC APIs.	2017-07-07 02:59:13 +00:00