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b993023ac9
Move the logic to constraint register from InstructionSelector to a utility function. It will be required by other passes in the GlobalISel pipeline. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290374 91177308-0d34-0410-b5e6-96231b3b80d8
46 lines
1.7 KiB
C++
46 lines
1.7 KiB
C++
//===- llvm/CodeGen/GlobalISel/Utils.cpp -------------------------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file This file implements the utility functions used by the GlobalISel
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/// pipeline.
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/GlobalISel/Utils.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#define DEBUG_TYPE "globalisel-utils"
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using namespace llvm;
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unsigned llvm::constrainOperandRegClass(
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const MachineFunction &MF, const TargetRegisterInfo &TRI,
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MachineRegisterInfo &MRI, const TargetInstrInfo &TII,
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const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II,
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unsigned Reg, unsigned OpIdx) {
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// Assume physical registers are properly constrained.
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assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
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"PhysReg not implemented");
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const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF);
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if (!RBI.constrainGenericRegister(Reg, *RegClass, MRI)) {
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unsigned NewReg = MRI.createVirtualRegister(RegClass);
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BuildMI(*InsertPt.getParent(), InsertPt, InsertPt.getDebugLoc(),
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TII.get(TargetOpcode::COPY), NewReg)
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.addReg(Reg);
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return NewReg;
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}
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return Reg;
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}
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