Jim Grosbach 28f08c93e7 ARM refactor away a bunch of VLD/VST pseudo instructions. ...

With the new composite physical registers to represent arbitrary pairs
of DPR registers, we don't need the pseudo-registers anymore. Get rid of
a bunch of them that use DPR register pairs and just use the real
instructions directly instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152045 91177308-0d34-0410-b5e6-96231b3b80d8

2012-03-05 19:33:30 +00:00

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Analysis

LVI: Recognize the form instcombine canonicalizes range checks into when forming constant ranges.

2012-03-02 15:34:43 +00:00

Archive

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AsmParser

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Bitcode

BitstreamWriter: Change primary output buffer to be a SmallVector instead of an

2012-02-29 20:31:09 +00:00

CodeGen

Make MCRegisterInfo available to the the MCInstPrinter.

2012-03-05 19:33:20 +00:00

DebugInfo

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ExecutionEngine

Fixed the 32-bit runtime dynamic loader to allocate

2012-03-01 00:15:29 +00:00

Linker

Include cctype for isdigit. Patch by Stephen Hines.

2012-03-03 09:36:58 +00:00

MC

Make MCRegisterInfo available to the the MCInstPrinter.

2012-03-05 19:33:20 +00:00

Object

[Object]

2012-03-01 22:19:54 +00:00

Support

Replace the hashing functions on APInt and APFloat with overloads of the

2012-03-04 12:02:57 +00:00

TableGen

Switch the TableGen record's string-based DenseMap key to use the new

2012-03-05 10:36:16 +00:00

Target

ARM refactor away a bunch of VLD/VST pseudo instructions.

2012-03-05 19:33:30 +00:00

Transforms

fix typos

2012-03-05 17:39:47 +00:00

VMCore

Replace the hashing functions on APInt and APFloat with overloads of the

2012-03-04 12:02:57 +00:00

CMakeLists.txt

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LLVMBuild.txt

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Makefile

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