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2a50eccea8
Before this patch, the register file was always updated at instruction creation time. That means, new read-after-write dependencies, and new temporary registers were allocated at instruction creation time. This patch refactors the code in InstrBuilder, and move all the logic that updates the register file into the dispatch unit. We only want to update the register file when instructions are effectively dispatched (not before). This refactoring also helps removing a bad dependency between the InstrBuilder and the DispatchUnit. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327514 91177308-0d34-0410-b5e6-96231b3b80d8
79 lines
2.2 KiB
C++
79 lines
2.2 KiB
C++
//===--------------------- Backend.cpp --------------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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///
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/// Implementation of class Backend which emulates an hardware OoO backend.
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///
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//===----------------------------------------------------------------------===//
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#include "Backend.h"
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#include "HWEventListener.h"
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#include "llvm/CodeGen/TargetSchedule.h"
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#include "llvm/Support/Debug.h"
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namespace mca {
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#define DEBUG_TYPE "llvm-mca"
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using namespace llvm;
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void Backend::addEventListener(HWEventListener *Listener) {
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if (Listener)
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Listeners.insert(Listener);
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}
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void Backend::runCycle(unsigned Cycle) {
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notifyCycleBegin(Cycle);
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while (SM.hasNext()) {
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InstRef IR = SM.peekNext();
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std::unique_ptr<Instruction> NewIS(
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IB->createInstruction(STI, IR.first, *IR.second));
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const InstrDesc &Desc = NewIS->getDesc();
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if (!DU->isAvailable(Desc.NumMicroOps) || !DU->canDispatch(Desc))
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break;
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Instruction *IS = NewIS.get();
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Instructions[IR.first] = std::move(NewIS);
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IS->setRCUTokenID(DU->dispatch(IR.first, IS, STI));
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SM.updateNext();
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}
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notifyCycleEnd(Cycle);
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}
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void Backend::notifyCycleBegin(unsigned Cycle) {
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DEBUG(dbgs() << "[E] Cycle begin: " << Cycle << '\n');
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for (HWEventListener *Listener : Listeners)
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Listener->onCycleBegin(Cycle);
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DU->cycleEvent(Cycle);
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HWS->cycleEvent(Cycle);
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}
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void Backend::notifyInstructionEvent(const HWInstructionEvent &Event) {
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for (HWEventListener *Listener : Listeners)
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Listener->onInstructionEvent(Event);
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}
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void Backend::notifyResourceAvailable(const ResourceRef &RR) {
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DEBUG(dbgs() << "[E] Resource Available: [" << RR.first << '.' << RR.second
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<< "]\n");
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for (HWEventListener *Listener : Listeners)
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Listener->onResourceAvailable(RR);
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}
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void Backend::notifyCycleEnd(unsigned Cycle) {
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DEBUG(dbgs() << "[E] Cycle end: " << Cycle << "\n\n");
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for (HWEventListener *Listener : Listeners)
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Listener->onCycleEnd(Cycle);
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}
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} // namespace mca.
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