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95780cccef
implementation of getReg() for arguments. MachineCodeEmitter.cpp: Fix using EBP with index, scale and no displacement (whew!) due to Chris. Printer.cpp: Fix printing out index and scale in memory references. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4998 91177308-0d34-0410-b5e6-96231b3b80d8
342 lines
11 KiB
C++
342 lines
11 KiB
C++
//===-- X86/Printer.cpp - Convert X86 code to human readable rep. ---------===//
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//
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// This file contains a printer that converts from our internal representation
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// of LLVM code to a nice human readable form that is suitable for debuggging.
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//
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "X86InstrInfo.h"
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#include "llvm/Pass.h"
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#include "llvm/Function.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "Support/Statistic.h"
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namespace {
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struct Printer : public FunctionPass {
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TargetMachine &TM;
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std::ostream &O;
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Printer(TargetMachine &tm, std::ostream &o) : TM(tm), O(o) {}
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bool runOnFunction(Function &F);
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};
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}
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/// createX86CodePrinterPass - Print out the specified machine code function to
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/// the specified stream. This function should work regardless of whether or
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/// not the function is in SSA form or not.
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///
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Pass *createX86CodePrinterPass(TargetMachine &TM, std::ostream &O) {
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return new Printer(TM, O);
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}
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/// runOnFunction - This uses the X86InstructionInfo::print method
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/// to print assembly for each instruction.
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bool Printer::runOnFunction (Function & F)
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{
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static unsigned bbnumber = 0;
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MachineFunction & MF = MachineFunction::get (&F);
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const MachineInstrInfo & MII = TM.getInstrInfo ();
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// Print out labels for the function.
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O << "\t.globl\t" << F.getName () << "\n";
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O << "\t.type\t" << F.getName () << ", @function\n";
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O << F.getName () << ":\n";
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// Print out code for the function.
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for (MachineFunction::const_iterator bb_i = MF.begin (), bb_e = MF.end ();
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bb_i != bb_e; ++bb_i)
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{
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// Print a label for the basic block.
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O << ".BB" << bbnumber++ << ":\n";
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for (MachineBasicBlock::const_iterator i_i = bb_i->begin (), i_e =
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bb_i->end (); i_i != i_e; ++i_i)
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{
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// Print the assembly for the instruction.
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O << "\t";
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MII.print(*i_i, O, TM);
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}
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}
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// We didn't modify anything.
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return false;
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}
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static bool isReg(const MachineOperand &MO) {
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return MO.getType() == MachineOperand::MO_VirtualRegister ||
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MO.getType() == MachineOperand::MO_MachineRegister;
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}
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static bool isImmediate(const MachineOperand &MO) {
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return MO.getType() == MachineOperand::MO_SignExtendedImmed ||
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MO.getType() == MachineOperand::MO_UnextendedImmed;
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}
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static bool isPCRelativeDisp(const MachineOperand &MO) {
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return MO.getType() == MachineOperand::MO_PCRelativeDisp;
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}
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static bool isScale(const MachineOperand &MO) {
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return isImmediate(MO) &&
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(MO.getImmedValue() == 1 || MO.getImmedValue() == 2 ||
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MO.getImmedValue() == 4 || MO.getImmedValue() == 8);
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}
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static bool isMem(const MachineInstr *MI, unsigned Op) {
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return Op+4 <= MI->getNumOperands() &&
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isReg(MI->getOperand(Op )) && isScale(MI->getOperand(Op+1)) &&
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isReg(MI->getOperand(Op+2)) && isImmediate(MI->getOperand(Op+3));
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}
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static void printOp(std::ostream &O, const MachineOperand &MO,
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const MRegisterInfo &RI) {
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switch (MO.getType()) {
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case MachineOperand::MO_VirtualRegister:
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if (Value *V = MO.getVRegValueOrNull()) {
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O << "<" << V->getName() << ">";
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return;
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}
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case MachineOperand::MO_MachineRegister:
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if (MO.getReg() < MRegisterInfo::FirstVirtualRegister)
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O << RI.get(MO.getReg()).Name;
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else
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O << "%reg" << MO.getReg();
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return;
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case MachineOperand::MO_SignExtendedImmed:
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case MachineOperand::MO_UnextendedImmed:
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O << (int)MO.getImmedValue();
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return;
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case MachineOperand::MO_PCRelativeDisp:
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O << "<" << MO.getVRegValue()->getName() << ">";
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return;
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default:
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O << "<unknown op ty>"; return;
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}
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}
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static const std::string sizePtr (const MachineInstrDescriptor &Desc) {
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switch (Desc.TSFlags & X86II::ArgMask) {
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case X86II::Arg8: return "BYTE PTR";
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case X86II::Arg16: return "WORD PTR";
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case X86II::Arg32: return "DWORD PTR";
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case X86II::Arg64: return "QWORD PTR";
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case X86II::Arg80: return "XWORD PTR";
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case X86II::Arg128: return "128BIT PTR"; // dunno what the real one is
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default: return "<SIZE?> PTR"; // crack being smoked
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}
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}
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static void printMemReference(std::ostream &O, const MachineInstr *MI,
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unsigned Op, const MRegisterInfo &RI) {
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assert(isMem(MI, Op) && "Invalid memory reference!");
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const MachineOperand &BaseReg = MI->getOperand(Op);
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const MachineOperand &Scale = MI->getOperand(Op+1);
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const MachineOperand &IndexReg = MI->getOperand(Op+2);
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const MachineOperand &Disp = MI->getOperand(Op+3);
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O << "[";
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bool NeedPlus = false;
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if (BaseReg.getReg()) {
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printOp(O, BaseReg, RI);
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NeedPlus = true;
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}
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if (IndexReg.getReg()) {
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if (NeedPlus) O << " + ";
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if (Scale.getImmedValue() != 1)
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O << Scale.getImmedValue() << "*";
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printOp(O, IndexReg, RI);
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NeedPlus = true;
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}
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if (Disp.getImmedValue()) {
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if (NeedPlus) O << " + ";
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printOp(O, Disp, RI);
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}
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O << "]";
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}
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// print - Print out an x86 instruction in intel syntax
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void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
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const TargetMachine &TM) const {
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unsigned Opcode = MI->getOpcode();
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const MachineInstrDescriptor &Desc = get(Opcode);
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switch (Desc.TSFlags & X86II::FormMask) {
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case X86II::RawFrm:
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// The accepted forms of Raw instructions are:
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// 1. nop - No operand required
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// 2. jmp foo - PC relative displacement operand
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//
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assert(MI->getNumOperands() == 0 ||
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(MI->getNumOperands() == 1 && isPCRelativeDisp(MI->getOperand(0))) &&
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"Illegal raw instruction!");
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O << getName(MI->getOpCode()) << " ";
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if (MI->getNumOperands() == 1) {
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printOp(O, MI->getOperand(0), RI);
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}
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O << "\n";
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return;
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case X86II::AddRegFrm: {
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// There are currently two forms of acceptable AddRegFrm instructions.
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// Either the instruction JUST takes a single register (like inc, dec, etc),
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// or it takes a register and an immediate of the same size as the register
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// (move immediate f.e.). Note that this immediate value might be stored as
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// an LLVM value, to represent, for example, loading the address of a global
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// into a register.
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//
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assert(isReg(MI->getOperand(0)) &&
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(MI->getNumOperands() == 1 ||
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(MI->getNumOperands() == 2 &&
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(MI->getOperand(1).getVRegValueOrNull() ||
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isImmediate(MI->getOperand(1))))) &&
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"Illegal form for AddRegFrm instruction!");
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unsigned Reg = MI->getOperand(0).getReg();
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O << getName(MI->getOpCode()) << " ";
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printOp(O, MI->getOperand(0), RI);
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if (MI->getNumOperands() == 2) {
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O << ", ";
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printOp(O, MI->getOperand(1), RI);
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}
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O << "\n";
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return;
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}
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case X86II::MRMDestReg: {
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// There are two acceptable forms of MRMDestReg instructions, those with 3
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// and 2 operands:
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//
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// 3 Operands: in this form, the first two registers (the destination, and
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// the first operand) should be the same, post register allocation. The 3rd
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// operand is an additional input. This should be for things like add
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// instructions.
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//
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// 2 Operands: this is for things like mov that do not read a second input
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//
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assert(isReg(MI->getOperand(0)) &&
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(MI->getNumOperands() == 2 ||
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(MI->getNumOperands() == 3 && isReg(MI->getOperand(1)))) &&
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isReg(MI->getOperand(MI->getNumOperands()-1))
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&& "Bad format for MRMDestReg!");
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if (MI->getNumOperands() == 3 &&
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MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
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O << "**";
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O << getName(MI->getOpCode()) << " ";
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printOp(O, MI->getOperand(0), RI);
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O << ", ";
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printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
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O << "\n";
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return;
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}
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case X86II::MRMDestMem: {
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// These instructions are the same as MRMDestReg, but instead of having a
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// register reference for the mod/rm field, it's a memory reference.
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//
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assert(isMem(MI, 0) && MI->getNumOperands() == 4+1 &&
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isReg(MI->getOperand(4)) && "Bad format for MRMDestMem!");
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O << getName(MI->getOpCode()) << " " << sizePtr (Desc) << " ";
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printMemReference(O, MI, 0, RI);
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O << ", ";
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printOp(O, MI->getOperand(4), RI);
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O << "\n";
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return;
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}
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case X86II::MRMSrcReg: {
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// There is a two forms that are acceptable for MRMSrcReg instructions,
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// those with 3 and 2 operands:
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//
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// 3 Operands: in this form, the last register (the second input) is the
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// ModR/M input. The first two operands should be the same, post register
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// allocation. This is for things like: add r32, r/m32
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//
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// 2 Operands: this is for things like mov that do not read a second input
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//
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assert(isReg(MI->getOperand(0)) &&
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isReg(MI->getOperand(1)) &&
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(MI->getNumOperands() == 2 ||
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(MI->getNumOperands() == 3 && isReg(MI->getOperand(2))))
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&& "Bad format for MRMDestReg!");
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if (MI->getNumOperands() == 3 &&
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MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
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O << "**";
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O << getName(MI->getOpCode()) << " ";
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printOp(O, MI->getOperand(0), RI);
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O << ", ";
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printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
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O << "\n";
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return;
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}
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case X86II::MRMSrcMem: {
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// These instructions are the same as MRMSrcReg, but instead of having a
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// register reference for the mod/rm field, it's a memory reference.
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//
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assert(isReg(MI->getOperand(0)) &&
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(MI->getNumOperands() == 1+4 && isMem(MI, 1)) ||
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(MI->getNumOperands() == 2+4 && isReg(MI->getOperand(1)) &&
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isMem(MI, 2))
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&& "Bad format for MRMDestReg!");
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if (MI->getNumOperands() == 2+4 &&
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MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
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O << "**";
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O << getName(MI->getOpCode()) << " ";
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printOp(O, MI->getOperand(0), RI);
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O << ", " << sizePtr (Desc) << " ";
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printMemReference(O, MI, MI->getNumOperands()-4, RI);
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O << "\n";
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return;
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}
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case X86II::MRMS0r: case X86II::MRMS1r:
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case X86II::MRMS2r: case X86II::MRMS3r:
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case X86II::MRMS4r: case X86II::MRMS5r:
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case X86II::MRMS6r: case X86II::MRMS7r: {
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// In this form, the following are valid formats:
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// 1. sete r
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// 2. cmp reg, immediate
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// 2. shl rdest, rinput <implicit CL or 1>
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// 3. sbb rdest, rinput, immediate [rdest = rinput]
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//
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assert(MI->getNumOperands() > 0 && MI->getNumOperands() < 4 &&
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isReg(MI->getOperand(0)) && "Bad MRMSxR format!");
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assert((MI->getNumOperands() != 2 ||
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isReg(MI->getOperand(1)) || isImmediate(MI->getOperand(1))) &&
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"Bad MRMSxR format!");
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assert((MI->getNumOperands() < 3 ||
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(isReg(MI->getOperand(1)) && isImmediate(MI->getOperand(2)))) &&
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"Bad MRMSxR format!");
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if (MI->getNumOperands() > 1 && isReg(MI->getOperand(1)) &&
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MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
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O << "**";
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O << getName(MI->getOpCode()) << " ";
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printOp(O, MI->getOperand(0), RI);
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if (isImmediate(MI->getOperand(MI->getNumOperands()-1))) {
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O << ", ";
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printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
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}
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O << "\n";
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return;
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}
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default:
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O << "\t\t\t-"; MI->print(O, TM); break;
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}
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}
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