llvm/lib/CodeGen
Jonas Paulsson 0b88d3e7ee [MachineVerifier] Analyze MachineMemOperands for mem-to-mem moves.
Since the verifier will give false reports if it incorrectly thinks MI is
loading or storing using an FI, it is necessary to scan memoperands and
find out how the FI is used in the instruction. This should be relatively
rare.

Needed to make CodeGen/SystemZ/spill-01.ll pass, which now runs with this flag.

Reviewed by Quentin Colombet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251620 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-29 08:28:35 +00:00
..
AsmPrinter ARM: support .watchos_version_min and .tvos_version_min. 2015-10-28 22:36:05 +00:00
MIRParser Fix PR 24724 - The implicit register verifier shouldn't assume certain operand 2015-09-10 14:04:34 +00:00
SelectionDAG [ValueTracking] Use !range metadata more aggressively in KnownBits 2015-10-28 03:20:15 +00:00
AggressiveAntiDepBreaker.cpp Revert "Simplify code. NFC." 2015-10-09 19:48:48 +00:00
AggressiveAntiDepBreaker.h
AllocationOrder.cpp
AllocationOrder.h
Analysis.cpp Remove assert(false) in favor of asserting the if conditional it is contained within. 2015-10-26 18:41:13 +00:00
AntiDepBreaker.h
AtomicExpandPass.cpp CodeGen: Start removing implicit conversions to/from list iterators, NFC 2015-10-09 16:54:49 +00:00
BasicTargetTransformInfo.cpp constify the Function parameter to the TTI creation callback and 2015-09-16 23:38:13 +00:00
BranchFolding.cpp Refactor: Simplify boolean conditional return statements in lib/CodeGen. 2015-10-24 23:11:13 +00:00
BranchFolding.h [WinEH] Permit branch folding in the face of funclets 2015-10-04 02:22:52 +00:00
CalcSpillWeights.cpp
CallingConvLower.cpp Arguments spilled on the stack before a function call may have 2015-09-29 10:12:57 +00:00
CMakeLists.txt [WinEH] Add a funclet layout pass 2015-09-17 20:45:18 +00:00
CodeGen.cpp [WinEH] Add a funclet layout pass 2015-09-17 20:45:18 +00:00
CodeGenPrepare.cpp Scalarizer for masked.gather and masked.scatter intrinsics. 2015-10-25 15:37:55 +00:00
CoreCLRGC.cpp
CriticalAntiDepBreaker.cpp MachineBasicBlock: Factor out common code into isReturnBlock() 2015-09-25 21:25:19 +00:00
CriticalAntiDepBreaker.h
DeadMachineInstructionElim.cpp Save LaneMask with livein registers 2015-09-09 18:08:03 +00:00
DFAPacketizer.cpp CodeGen: Remove a few more ilist iterator implicit conversions, NFC 2015-10-09 18:44:40 +00:00
DwarfEHPrepare.cpp [WinEH] Recognize CoreCLR personality function 2015-10-06 20:28:16 +00:00
EarlyIfConversion.cpp
EdgeBundles.cpp
ErlangGC.cpp
ExecutionDepsFix.cpp CodeGen: Start removing implicit conversions to/from list iterators, NFC 2015-10-09 16:54:49 +00:00
ExpandISelPseudos.cpp CodeGen: Remove a few more ilist iterator implicit conversions, NFC 2015-10-09 18:44:40 +00:00
ExpandPostRAPseudos.cpp
FaultMaps.cpp
FuncletLayout.cpp [WinEH] Update CATCHRET's operand to match its successor 2015-10-05 20:09:16 +00:00
GCMetadata.cpp
GCMetadataPrinter.cpp
GCRootLowering.cpp CodeGen: Remove a few more ilist iterator implicit conversions, NFC 2015-10-09 18:44:40 +00:00
GCStrategy.cpp
GlobalMerge.cpp CodeGen: Use range-based for in GlobalMerge, NFC 2015-10-09 18:57:47 +00:00
IfConversion.cpp CodeGen: Remove more ilist iterator implicit conversions, NFC 2015-10-09 19:13:58 +00:00
ImplicitNullChecks.cpp
InlineSpiller.cpp [PM/AA] Rebuild LLVM's alias analysis infrastructure in a way compatible 2015-09-09 17:55:00 +00:00
InterferenceCache.cpp CodeGen: Remove more ilist iterator implicit conversions, NFC 2015-10-09 19:13:58 +00:00
InterferenceCache.h
InterleavedAccessPass.cpp
IntrinsicLowering.cpp CodeGen: Remove more ilist iterator implicit conversions, NFC 2015-10-09 19:13:58 +00:00
LatencyPriorityQueue.cpp
LexicalScopes.cpp
LiveDebugVariables.cpp Refactor: Simplify boolean conditional return statements in lib/CodeGen. 2015-10-24 23:11:13 +00:00
LiveDebugVariables.h
LiveInterval.cpp TargetRegisterInfo: Introduce PrintLaneMask. 2015-09-25 21:51:24 +00:00
LiveIntervalAnalysis.cpp CodeGen: Remove more ilist iterator implicit conversions, NFC 2015-10-09 19:13:58 +00:00
LiveIntervalUnion.cpp
LivePhysRegs.cpp LivePhysRegs: Fix live-outs of return blocks 2015-09-25 23:50:53 +00:00
LiveRangeCalc.cpp TargetRegisterInfo: Add typedef unsigned LaneBitmask and use it where apropriate; NFC 2015-09-25 21:51:14 +00:00
LiveRangeCalc.h TargetRegisterInfo: Add typedef unsigned LaneBitmask and use it where apropriate; NFC 2015-09-25 21:51:14 +00:00
LiveRangeEdit.cpp TargetRegisterInfo: Add typedef unsigned LaneBitmask and use it where apropriate; NFC 2015-09-25 21:51:14 +00:00
LiveRegMatrix.cpp TargetRegisterInfo: Introduce PrintLaneMask. 2015-09-25 21:51:24 +00:00
LiveStackAnalysis.cpp
LiveVariables.cpp CodeGen: Remove more ilist iterator implicit conversions, NFC 2015-10-09 19:13:58 +00:00
LLVMBuild.txt
LLVMTargetMachine.cpp constify the Function parameter to the TTI creation callback and 2015-09-16 23:38:13 +00:00
LocalStackSlotAllocation.cpp CodeGen: Remove more ilist iterator implicit conversions, NFC 2015-10-09 19:13:58 +00:00
MachineBasicBlock.cpp Create a new interface addSuccessorWithoutWeight(MBB*) in MBB to add successors when optimization is disabled. 2015-10-27 17:59:36 +00:00
MachineBlockFrequencyInfo.cpp CodeGen: Avoid ilist iterator implicit conversions in a few more places, NFC 2015-10-09 19:23:20 +00:00
MachineBlockPlacement.cpp Enhance loop rotation with existence of profile data in MachineBlockPlacement pass. 2015-10-19 23:16:40 +00:00
MachineBranchProbabilityInfo.cpp
MachineCombiner.cpp Fix Clang-tidy modernize-use-nullptr warnings in source directories and generated files; other minor cleanups. 2015-10-06 23:24:35 +00:00
MachineCopyPropagation.cpp
MachineCSE.cpp [PM/AA] Rebuild LLVM's alias analysis infrastructure in a way compatible 2015-09-09 17:55:00 +00:00
MachineDominanceFrontier.cpp
MachineDominators.cpp
MachineFunction.cpp CodeGen: Continue removing ilist iterator implicit conversions 2015-10-09 19:40:45 +00:00
MachineFunctionAnalysis.cpp
MachineFunctionPass.cpp [PM/AA] Rebuild LLVM's alias analysis infrastructure in a way compatible 2015-09-09 17:55:00 +00:00
MachineFunctionPrinterPass.cpp
MachineInstr.cpp CodeGen: Continue removing ilist iterator implicit conversions 2015-10-09 19:40:45 +00:00
MachineInstrBundle.cpp
MachineLICM.cpp CodeGen: Continue removing ilist iterator implicit conversions 2015-10-09 19:40:45 +00:00
MachineLoopInfo.cpp CodeGen: Continue removing ilist iterator implicit conversions 2015-10-09 19:40:45 +00:00
MachineModuleInfo.cpp [WinEH] Remove more dead code 2015-10-10 00:04:29 +00:00
MachineModuleInfoImpls.cpp
MachinePassRegistry.cpp
MachinePostDominators.cpp
MachineRegionInfo.cpp
MachineRegisterInfo.cpp Refactor: Simplify boolean conditional return statements in lib/CodeGen. 2015-10-24 23:11:13 +00:00
MachineScheduler.cpp Revert "ScheduleDAGInstrs: Remove IsPostRA flag" 2015-10-29 05:06:41 +00:00
MachineSink.cpp Refine the definition of convergent to only disallow the addition of new control dependencies. 2015-10-09 18:06:13 +00:00
MachineSSAUpdater.cpp
MachineTraceMetrics.cpp
MachineVerifier.cpp [MachineVerifier] Analyze MachineMemOperands for mem-to-mem moves. 2015-10-29 08:28:35 +00:00
Makefile
MIRPrinter.cpp TargetRegisterInfo: Introduce PrintLaneMask. 2015-09-25 21:51:24 +00:00
MIRPrinter.h
MIRPrintingPass.cpp Re-commit r247216: "Fix Clang-tidy misc-use-override warnings, other minor fixes" 2015-09-10 16:49:58 +00:00
module.modulemap
OcamlGC.cpp
OptimizePHIs.cpp
ParallelCG.cpp
Passes.cpp Enable verifier after PeepholeOptimizer 2015-10-12 17:43:56 +00:00
PeepholeOptimizer.cpp Refactor: Simplify boolean conditional return statements in lib/CodeGen. 2015-10-24 23:11:13 +00:00
PHIElimination.cpp
PHIEliminationUtils.cpp
PHIEliminationUtils.h
PostRASchedulerList.cpp CodeGen: Use range-based for in PostRAScheduler, NFC 2015-10-09 21:05:00 +00:00
ProcessImplicitDefs.cpp CodeGen: Avoid more ilist iterator implicit conversions, NFC 2015-10-09 21:08:19 +00:00
PrologEpilogInserter.cpp CodeGen: Avoid more ilist iterator implicit conversions, NFC 2015-10-09 21:08:19 +00:00
PseudoSourceValue.cpp Refactor: Simplify boolean conditional return statements in lib/CodeGen. 2015-10-24 23:11:13 +00:00
README.txt
RegAllocBase.cpp
RegAllocBase.h
RegAllocBasic.cpp [PM/AA] Rebuild LLVM's alias analysis infrastructure in a way compatible 2015-09-09 17:55:00 +00:00
RegAllocFast.cpp Save LaneMask with livein registers 2015-09-09 18:08:03 +00:00
RegAllocGreedy.cpp [PM/AA] Rebuild LLVM's alias analysis infrastructure in a way compatible 2015-09-09 17:55:00 +00:00
RegAllocPBQP.cpp [PM/AA] Rebuild LLVM's alias analysis infrastructure in a way compatible 2015-09-09 17:55:00 +00:00
RegisterClassInfo.cpp
RegisterCoalescer.cpp CodeGen: Avoid more ilist iterator implicit conversions, NFC 2015-10-09 21:08:19 +00:00
RegisterCoalescer.h
RegisterPressure.cpp Revert "RegisterPressure: allocatable physreg uses are always kills" 2015-10-19 17:44:22 +00:00
RegisterScavenging.cpp TargetRegisterInfo: Add typedef unsigned LaneBitmask and use it where apropriate; NFC 2015-09-25 21:51:14 +00:00
ScheduleDAG.cpp
ScheduleDAGInstrs.cpp Revert "ScheduleDAGInstrs: Remove IsPostRA flag" 2015-10-29 05:06:41 +00:00
ScheduleDAGPrinter.cpp Make the SelectionDAG graph printer use SDNode::PersistentId labels. 2015-10-27 23:09:03 +00:00
ScoreboardHazardRecognizer.cpp
ShadowStackGC.cpp
ShadowStackGCLowering.cpp CodeGen: Avoid more ilist iterator implicit conversions, NFC 2015-10-09 21:08:19 +00:00
ShrinkWrap.cpp [ShrinkWrap] Refactor the handling of infinite loop in the analysis. 2015-09-17 23:21:34 +00:00
SjLjEHPrepare.cpp CodeGen: Remove implicit ilist iterator conversions, NFC 2015-10-09 22:56:24 +00:00
SlotIndexes.cpp CodeGen: Continue removing ilist iterator implicit conversions 2015-10-09 19:40:45 +00:00
Spiller.h
SpillPlacement.cpp CodeGen: Remove implicit ilist iterator conversions, NFC 2015-10-09 22:56:24 +00:00
SpillPlacement.h
SplitKit.cpp CodeGen: Remove implicit ilist iterator conversions, NFC 2015-10-09 22:56:24 +00:00
SplitKit.h
StackColoring.cpp
StackMapLivenessAnalysis.cpp
StackMaps.cpp
StackProtector.cpp Refactor: Simplify boolean conditional return statements in lib/CodeGen. 2015-10-24 23:11:13 +00:00
StackSlotColoring.cpp
StatepointExampleGC.cpp
TailDuplication.cpp Tail duplication can mix incompatible registers in phi nodes 2015-10-21 02:40:06 +00:00
TargetFrameLoweringImpl.cpp HHVM calling conventions. 2015-09-29 22:09:16 +00:00
TargetInstrInfo.cpp Refactor: Simplify boolean conditional return statements in lib/CodeGen. 2015-10-24 23:11:13 +00:00
TargetLoweringBase.cpp [safestack] Fast access to the unsafe stack pointer on AArch64/Android. 2015-10-26 18:28:25 +00:00
TargetLoweringObjectFileImpl.cpp Sink COFF.h MC include into .cpp files 2015-09-03 16:41:50 +00:00
TargetOptionsImpl.cpp
TargetRegisterInfo.cpp TargetRegisterInfo: Introduce PrintLaneMask. 2015-09-25 21:51:24 +00:00
TargetSchedule.cpp
TwoAddressInstructionPass.cpp CodeGen: Remove implicit ilist iterator conversions, NFC 2015-10-09 22:56:24 +00:00
UnreachableBlockElim.cpp CodeGen: Remove implicit ilist iterator conversions, NFC 2015-10-09 22:56:24 +00:00
VirtRegMap.cpp CodeGen: Remove implicit ilist iterator conversions, NFC 2015-10-09 22:56:24 +00:00
WinEHPrepare.cpp [WinEH] Fix CatchRetSuccessorColorMap accounting 2015-10-16 21:22:54 +00:00

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str r4, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelihood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvements:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.