Chad Rosier 2f2d1d7ec0 [fast-isel] HandlePHINodesInSuccessorBlocks() can promite i8 and i16 types too. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149730 91177308-0d34-0410-b5e6-96231b3b80d8

2012-02-04 00:39:19 +00:00

..

CMakeLists.txt

fix cmake

2012-02-01 22:28:29 +00:00

DAGCombiner.cpp

The type-legalizer often scalarizes code. One of the common patterns is extract-and-truncate.

2012-02-03 13:18:25 +00:00

FastISel.cpp

[fast-isel] HandlePHINodesInSuccessorBlocks() can promite i8 and i16 types too.

2012-02-04 00:39:19 +00:00

FunctionLoweringInfo.cpp

Remove the eh.exception and eh.selector intrinsics. Also remove a hack to copy

2012-01-31 01:46:13 +00:00

InstrEmitter.cpp

Handle all live physreg defs in the same place.

2012-02-03 20:43:35 +00:00

InstrEmitter.h

Simplify EXTRACT_SUBREG emission.

2011-10-05 20:26:40 +00:00

LegalizeDAG.cpp

use ConstantVector::getSplat in a few places.

2012-01-25 06:02:56 +00:00

LegalizeFloatTypes.cpp

Added invariant field to the DAG.getLoad method and changed all calls.

2011-11-08 18:42:53 +00:00

LegalizeIntegerTypes.cpp

More dead code removal (using -Wunreachable-code)

2012-01-20 21:51:11 +00:00

LegalizeTypes.cpp

Remove unnecessary default cases in switches that cover all enum values.

2012-01-10 16:47:17 +00:00

LegalizeTypes.h

1. Fix the widening of SETCC in WidenVecOp_SETCC. Use the correct return CC type.

2011-10-21 11:42:07 +00:00

LegalizeTypesGeneric.cpp

Remove unnecessary default cases in switches that cover all enum values.

2012-01-10 16:47:17 +00:00

LegalizeVectorOps.cpp

Initial CodeGen support for CTTZ/CTLZ where a zero input produces an

2011-12-13 01:56:10 +00:00

LegalizeVectorTypes.cpp

On AVX, we can load v8i32 at a time. The bug happens when two uneven loads are used.

2012-01-11 20:19:17 +00:00

LLVMBuild.txt

LLVMBuild: Remove trailing newline, which irked me.

2011-12-12 19:48:00 +00:00

Makefile

make -fno-rtti the default unless a directory builds with REQUIRES_RTTI.

2010-01-24 20:43:08 +00:00

ResourcePriorityQueue.cpp

VLIW specific scheduler framework that utilizes deterministic finite automaton (DFA).

2012-02-01 22:13:57 +00:00

ScheduleDAGFast.cpp

- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and

2011-06-28 19:10:37 +00:00

ScheduleDAGRRList.cpp

Make sure we correctly set LiveRegGens when a call is unscheduled. <rdar://problem/10460321>. No testcase because this is very sensitive to scheduling.

2011-12-07 22:24:28 +00:00

ScheduleDAGSDNodes.cpp

Rename TargetSubtarget to TargetSubtargetInfo for consistency.

2011-07-01 21:01:15 +00:00

ScheduleDAGSDNodes.h

Add a RegisterMaskSDNode class.

2012-01-18 23:52:12 +00:00

ScheduleDAGVLIW.cpp

VLIW specific scheduler framework that utilizes deterministic finite automaton (DFA).

2012-02-01 22:13:57 +00:00

SDNodeDbgValue.h

Do not lose debug info of an inlined function argument even if the argument is only used through GEPs.

2011-02-18 22:43:42 +00:00

SDNodeOrdering.h

Allow 0 as an order number. Don't assign an order to formal arguments.

2009-12-22 21:35:02 +00:00

SelectionDAG.cpp

Revert Chris' commits up to r149348 that started causing VMCoreTests unit test to fail.

2012-02-01 04:51:17 +00:00

SelectionDAGBuilder.cpp

SwitchInst refactoring.

2012-02-01 07:49:51 +00:00

SelectionDAGBuilder.h

SwitchInst refactoring.

2012-02-01 07:49:51 +00:00

SelectionDAGISel.cpp

VLIW specific scheduler framework that utilizes deterministic finite automaton (DFA).

2012-02-01 22:13:57 +00:00

SelectionDAGPrinter.cpp

drop unneeded config.h includes

2011-12-22 23:04:07 +00:00

TargetLowering.cpp

Use the correct ShiftAmtTy for creating shifts after legalization. PR11881. Not committing a testcase because I think it will be too fragile.

2012-01-31 01:08:03 +00:00

TargetSelectionDAGInfo.cpp

Implement a bunch more TargetSelectionDAGInfo infrastructure.

2010-05-11 17:31:57 +00:00