David Bolvansky 125c8f987d [DAGCombiner] Fold 0 div/rem X to 0 ...

Reviewers: RKSimon, spatel, javed.absar, craig.topper, t.p.northover

Reviewed By: RKSimon

Subscribers: craig.topper, llvm-commits

Differential Revision: https://reviews.llvm.org/D52504

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345721 91177308-0d34-0410-b5e6-96231b3b80d8

2018-10-31 14:18:57 +00:00

..

AArch64

[ARM64] [Windows] Exception handling support in frame lowering

2018-10-31 09:27:01 +00:00

AMDGPU

AMDGPU: Rewrite SILowerI1Copies to always stay on SALU

2018-10-31 13:27:08 +00:00

ARC

…

ARM

MachineOperand/MIParser: Do not print debug-use flag, infer it

2018-10-30 23:28:27 +00:00

AVR

[AVR] Fix the 'call.ll' CodeGen test

2018-10-10 03:21:42 +00:00

BPF

[bpf] Test case for symbol information in object file

2018-09-22 17:31:01 +00:00

Generic

[MIR] Simplify and move MIR test

2018-10-26 16:00:29 +00:00

Hexagon

MachineOperand/MIParser: Do not print debug-use flag, infer it

2018-10-30 23:28:27 +00:00

Inputs

…

Lanai

Remove SETCCE use from Lanai's backend

2018-06-03 12:56:24 +00:00

Mips

[DAGCombiner] Improve X div/rem Y fold if single bit element type

2018-10-30 09:07:22 +00:00

MIR

MachineOperand/MIParser: Do not print debug-use flag, infer it

2018-10-30 23:28:27 +00:00

MSP430

[DAGCombiner] Add X / X -> 1 & X % X -> 0 folds (test tweaks)

2018-08-29 11:18:14 +00:00

Nios2

[Nios2] Arithmetic instructions for R1 and R2 ISA.

2018-01-09 11:15:08 +00:00

NVPTX

[NVPTX] Implement isLegalToVectorizeLoadChain

2018-08-27 17:29:43 +00:00

PowerPC

MachineOperand/MIParser: Do not print debug-use flag, infer it

2018-10-30 23:28:27 +00:00

RISCV

[RISCV] Eliminate unnecessary masking of promoted shift amounts

2018-10-12 23:18:52 +00:00

SPARC

Relax fast register allocator related test cases; NFC

2018-10-29 20:10:42 +00:00

SystemZ

[SchedModel] Fix for read advance cycles with implicit pseudo operands.

2018-10-30 15:04:40 +00:00

Thumb

[ARM] Make InstrEmitter mark CPSR defs dead for Thumb1.

2018-10-26 19:32:24 +00:00

Thumb2

[SchedModel] Fix for read advance cycles with implicit pseudo operands.

2018-10-30 15:04:40 +00:00

WebAssembly

[WebAssembly] Lower away condition truncations for scalar selects

2018-10-29 18:38:12 +00:00

WinCFGuard

[COFF] Emit @feat.00 on 64-bit and set the CFG bit when emitting guardcf tables

2018-09-19 09:58:30 +00:00

WinEH

[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.

2018-05-09 02:40:45 +00:00

X86

[DAGCombiner] Fold 0 div/rem X to 0

2018-10-31 14:18:57 +00:00

XCore

Relax fast register allocator related test cases; NFC

2018-10-29 20:10:42 +00:00