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304d0f3076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19764 91177308-0d34-0410-b5e6-96231b3b80d8
269 lines
9.5 KiB
C++
269 lines
9.5 KiB
C++
//===- PPC64RegisterInfo.cpp - PowerPC64 Register Information ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the PowerPC64 implementation of the MRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "reginfo"
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#include "Alpha.h"
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#include "AlphaInstrBuilder.h"
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#include "AlphaRegisterInfo.h"
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#include "llvm/Constants.h"
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#include "llvm/Type.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/Target/TargetFrameInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/ADT/STLExtras.h"
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#include <cstdlib>
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#include <iostream>
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using namespace llvm;
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AlphaRegisterInfo::AlphaRegisterInfo()
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: AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP)
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{
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}
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static const TargetRegisterClass *getClass(unsigned SrcReg) {
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if (Alpha::FPRCRegisterClass->contains(SrcReg))
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return Alpha::FPRCRegisterClass;
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assert(Alpha::GPRCRegisterClass->contains(SrcReg) && "Reg not FPR or GPR");
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return Alpha::GPRCRegisterClass;
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}
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void
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AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, int FrameIdx) const {
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std::cerr << "Trying to store " << getPrettyName(SrcReg) << " to " << FrameIdx << "\n";
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//BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
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BuildMI(MBB, MI, Alpha::STQ, 3).addReg(SrcReg).addImm(FrameIdx * 8).addReg(Alpha::R30);
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// assert(0 && "TODO");
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}
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void
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AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIdx) const{
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std::cerr << "Trying to load " << getPrettyName(DestReg) << " to " << FrameIdx << "\n";
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//BuildMI(MBB, MI, Alpha::WTF, 0, DestReg);
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BuildMI(MBB, MI, Alpha::LDQ, 2, DestReg).addImm(FrameIdx * 8).addReg(Alpha::R30);
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// assert(0 && "TODO");
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}
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void AlphaRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *RC) const {
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// std::cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n";
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if (RC == Alpha::GPRCRegisterClass) {
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BuildMI(MBB, MI, Alpha::BIS, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
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// } else if (RC == Alpha::FPRCRegisterClass) {
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// BuildMI(MBB, MI, PPC::FMR, 1, DestReg).addReg(SrcReg);
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} else {
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std::cerr << "Attempt to copy register that is not GPR or FPR";
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abort();
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}
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}
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//===----------------------------------------------------------------------===//
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// Stack Frame Processing methods
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//===----------------------------------------------------------------------===//
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// hasFP - Return true if the specified function should have a dedicated frame
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// pointer register. This is true if the function has variable sized allocas or
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// if frame pointer elimination is disabled.
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//
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static bool hasFP(MachineFunction &MF) {
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MachineFrameInfo *MFI = MF.getFrameInfo();
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return MFI->hasVarSizedObjects();
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}
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void AlphaRegisterInfo::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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if (hasFP(MF)) {
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assert(0 && "TODO");
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// If we have a frame pointer, turn the adjcallstackup instruction into a
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// 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
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// <amt>'
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MachineInstr *Old = I;
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unsigned Amount = Old->getOperand(0).getImmedValue();
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if (Amount != 0) {
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// We need to keep the stack aligned properly. To do this, we round the
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// amount of space needed for the outgoing arguments up to the next
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// alignment boundary.
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unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
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Amount = (Amount+Align-1)/Align*Align;
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MachineInstr *New;
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// if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
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// New=BuildMI(X86::SUB32ri, 1, X86::ESP, MachineOperand::UseAndDef)
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// .addZImm(Amount);
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// } else {
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// assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
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// New=BuildMI(X86::ADD32ri, 1, X86::ESP, MachineOperand::UseAndDef)
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// .addZImm(Amount);
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// }
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// Replace the pseudo instruction with a new instruction...
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MBB.insert(I, New);
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}
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}
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MBB.erase(I);
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}
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void
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AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
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assert(0 && "TODO");
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// unsigned i = 0;
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// MachineInstr &MI = *II;
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// MachineBasicBlock &MBB = *MI.getParent();
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// MachineFunction &MF = *MBB.getParent();
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// while (!MI.getOperand(i).isFrameIndex()) {
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// ++i;
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// assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
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// }
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// int FrameIndex = MI.getOperand(i).getFrameIndex();
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// // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
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// MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1);
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// // Take into account whether it's an add or mem instruction
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// unsigned OffIdx = (i == 2) ? 1 : 2;
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// // Now add the frame object offset to the offset from r1.
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// int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
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// MI.getOperand(OffIdx).getImmedValue();
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// // If we're not using a Frame Pointer that has been set to the value of the
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// // SP before having the stack size subtracted from it, then add the stack size
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// // to Offset to get the correct offset.
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// Offset += MF.getFrameInfo()->getStackSize();
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// if (Offset > 32767 || Offset < -32768) {
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// // Insert a set of r0 with the full offset value before the ld, st, or add
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// MachineBasicBlock *MBB = MI.getParent();
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// MBB->insert(II, BuildMI(PPC::LIS, 1, PPC::R0).addSImm(Offset >> 16));
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// MBB->insert(II, BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
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// .addImm(Offset));
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// // convert into indexed form of the instruction
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// // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
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// // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
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// unsigned NewOpcode =
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// const_cast<std::map<unsigned, unsigned>& >(ImmToIdxMap)[MI.getOpcode()];
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// assert(NewOpcode && "No indexed form of load or store available!");
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// MI.setOpcode(NewOpcode);
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// MI.SetMachineOperandReg(1, MI.getOperand(i).getReg());
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// MI.SetMachineOperandReg(2, PPC::R0);
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// } else {
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// MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_SignExtendedImmed,
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// Offset);
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// }
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}
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void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const {
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MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
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MachineBasicBlock::iterator MBBI = MBB.begin();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MachineInstr *MI;
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//handle GOP offset
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MI = BuildMI(Alpha::LDGP, 0);
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MBB.insert(MBBI, MI);
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// Get the number of bytes to allocate from the FrameInfo
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unsigned NumBytes = MFI->getStackSize();
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// Do we need to allocate space on the stack?
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if (NumBytes == 0) return;
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// Add the size of R30 to NumBytes size for the store of R30 to the
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// stack
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// std::cerr << "Spillsize of R30 is " << getSpillSize(Alpha::R30) << "\n";
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// NumBytes = NumBytes + getSpillSize(Alpha::R30)/8;
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// Update frame info to pretend that this is part of the stack...
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MFI->setStackSize(NumBytes);
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// adjust stack pointer: r30 -= numbytes
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if (NumBytes <= 32000) //FIXME: do this better
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{
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MI=BuildMI(Alpha::LDA, 2, Alpha::R30).addImm(-NumBytes).addReg(Alpha::R30);
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MBB.insert(MBBI, MI);
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} else {
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std::cerr << "Too big a stack frame\n";
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abort();
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}
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}
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void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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MachineBasicBlock::iterator MBBI = prior(MBB.end());
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MachineInstr *MI;
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assert((MBBI->getOpcode() == Alpha::RET || MBBI->getOpcode() == Alpha::RETURN) &&
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"Can only insert epilog into returning blocks");
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// Get the number of bytes allocated from the FrameInfo...
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unsigned NumBytes = MFI->getStackSize();
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if (NumBytes != 0)
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{
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if (NumBytes <= 32000) //FIXME: do this better
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{
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MI=BuildMI(Alpha::LDA, 2, Alpha::R30).addImm(NumBytes).addReg(Alpha::R30);
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MBB.insert(MBBI, MI);
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} else {
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std::cerr << "Too big a stack frame\n";
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abort();
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}
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}
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}
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#include "AlphaGenRegisterInfo.inc"
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const TargetRegisterClass*
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AlphaRegisterInfo::getRegClassForType(const Type* Ty) const {
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switch (Ty->getTypeID()) {
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default: assert(0 && "Invalid type to getClass!");
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case Type::BoolTyID:
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case Type::SByteTyID:
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case Type::UByteTyID:
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case Type::ShortTyID:
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case Type::UShortTyID:
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case Type::IntTyID:
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case Type::UIntTyID:
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case Type::PointerTyID:
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case Type::LongTyID:
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case Type::ULongTyID: return &GPRCInstance;
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case Type::FloatTyID:
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case Type::DoubleTyID: return &FPRCInstance;
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}
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}
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std::string AlphaRegisterInfo::getPrettyName(unsigned reg)
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{
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std::string s(RegisterDescriptors[reg].Name);
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return s;
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}
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