RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2024-12-28 15:33:16 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity
3115047182
llvm/lib/Target/AArch64
History
Amara Emerson 2f21452ba1 [AArch64] Fix NZCV reg live-in bug in F128CSEL codegen. 
When generating the IfTrue basic block during the F128CSEL pseudo-instruction
handling, the NZCV live-in for the newly created BB wasn't being added. This
caused a fault during MI-sched/live range calculation when the predecessor
for the fall-through BB didn't have a live-in for phys-reg as expected.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193316 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-24 08:28:24 +00:00
..
AsmParser Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem). 2013-10-10 17:00:52 +00:00
Disassembler Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem). 2013-10-10 17:00:52 +00:00
InstPrinter Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem). 2013-10-10 17:00:52 +00:00
MCTargetDesc Add a MCAsmInfoELF class and factor some code into it. 2013-10-16 01:34:32 +00:00
TargetInfo
Utils Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem). 2013-10-10 17:00:52 +00:00
AArch64.h
AArch64.td
AArch64AsmPrinter.cpp
AArch64AsmPrinter.h
AArch64BranchFixupPass.cpp
AArch64CallingConv.td
AArch64FrameLowering.cpp
AArch64FrameLowering.h
AArch64InstrFormats.td [AArch64] Add support for NEON scalar three register different instruction 2013-10-17 18:12:29 +00:00
AArch64InstrInfo.cpp
AArch64InstrInfo.h
AArch64InstrInfo.td
AArch64InstrNEON.td [AArch64] Add the constraint to NEON scalar mla/mls instructions. 2013-10-21 20:11:47 +00:00
AArch64ISelDAGToDAG.cpp Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem). 2013-10-10 17:00:52 +00:00
AArch64ISelLowering.cpp [AArch64] Fix NZCV reg live-in bug in F128CSEL codegen. 2013-10-24 08:28:24 +00:00
AArch64ISelLowering.h Implement aarch64 neon instruction set AdvSIMD (copy). 2013-10-11 02:33:55 +00:00
AArch64MachineFunctionInfo.cpp
AArch64MachineFunctionInfo.h
AArch64MCInstLower.cpp
AArch64RegisterInfo.cpp
AArch64RegisterInfo.h
AArch64RegisterInfo.td Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem). 2013-10-10 17:00:52 +00:00
AArch64Schedule.td
AArch64SelectionDAGInfo.cpp
AArch64SelectionDAGInfo.h
AArch64Subtarget.cpp
AArch64Subtarget.h AArch64: enable MISched by default. 2013-10-09 07:53:57 +00:00
AArch64TargetMachine.cpp
AArch64TargetMachine.h
AArch64TargetObjectFile.cpp
AArch64TargetObjectFile.h
CMakeLists.txt
LLVMBuild.txt
Makefile
README.txt

README.txt 

This file will contain changes that need to be made before AArch64 can become an
officially supported target. Currently a placeholder.