Adrian Prantl 3517640443 Reapply an improved version of r180816/180817. ... Change the informal convention of DBG_VALUE machine instructions so that we can express a register-indirect address with an offset of 0. The old convention was that a DBG_VALUE is a register-indirect value if the offset (operand 1) is nonzero. The new convention is that a DBG_VALUE is register-indirect if the first operand is a register and the second operand is an immediate. For plain register values the combination reg, reg is used. MachineInstrBuilder::BuildMI knows how to build the new DBG_VALUES. rdar://problem/13658587 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185966 91177308-0d34-0410-b5e6-96231b3b80d8		2013-07-09 20:28:37 +00:00
..
AArch64	AArch64/PowerPC/SystemZ/X86: This patch fixes the interface, usage, and all	2013-07-09 18:16:56 +00:00
ARM	Add a comment to this change, requested by Eric Christopher.	2013-07-08 19:52:51 +00:00
CPP
Generic	Debug Info: clean up usage of Verify.	2013-06-28 05:43:10 +00:00
Hexagon
Inputs
MBlaze
Mips	[mips] Fix test case to check that mips64 instructions are generated.	2013-07-01 20:18:58 +00:00
MSP430	Really fix the test. Sorry for the breakage...	2013-07-01 19:51:36 +00:00
NVPTX	[NVPTX] Add support for module-scope inline asm	2013-07-01 13:00:14 +00:00
PowerPC	WidenVecRes_BUILD_VECTOR must use the first operand's type	2013-07-09 18:55:10 +00:00
R600	R600: Do not predicated basic block with multiple alu clause	2013-07-09 15:03:33 +00:00
SI
SPARC	Switch spill weights from a basic loop depth estimation to BlockFrequencyInfo.	2013-06-17 19:00:36 +00:00
SystemZ	[SystemZ] Use MVC for simple load/store pairs	2013-07-09 09:46:39 +00:00
Thumb
Thumb2	ARM: allow predicated barriers in Thumb mode	2013-06-26 16:52:32 +00:00
X86	Reapply an improved version of r180816/180817.	2013-07-09 20:28:37 +00:00
XCore	[XCore] Add ISel pattern for LDWCP	2013-07-03 07:48:50 +00:00