Jim Grosbach 383a810b12 ARM: Constrain regclass for TSTri instruction. ...

Get the register class right for the TST instruction. This keeps the
machine verifier happy, enabling us to turn it on for another test.

rdar://12594152

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189274 91177308-0d34-0410-b5e6-96231b3b80d8

2013-08-26 20:22:05 +00:00

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AArch64

A minor change for an obvous problem caused by r188451:

2013-08-21 17:47:53 +00:00

ARM

ARM: Constrain regclass for TSTri instruction.

2013-08-26 20:22:05 +00:00

CPP

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Generic

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Hexagon

TBAA: remove !tbaa from testing cases when they are not needed.

2013-08-21 22:20:53 +00:00

Inputs

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Mips

Start to add the LLVM builtins to the mips16 exclusion lists for fp.

2013-08-25 02:40:25 +00:00

MSP430

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NVPTX

[NVPTX] Re-enable assembly printing support for inline assembly

2013-08-24 01:17:23 +00:00

PowerPC

[PowerPC] More fast-isel chunks (returns and integer extends)

2013-08-26 19:42:51 +00:00

R600

SelectionDAG: Remove unnecessary uses of TargetLowering::getPointerTy()

2013-08-26 15:06:10 +00:00

SPARC

[Sparc] Add long double (f128) instructions to sparc backend.

2013-08-25 18:30:06 +00:00

SystemZ

[SystemZ] Add basic prefetch support

2013-08-23 11:36:42 +00:00

Thumb

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Thumb2

ARM: make sure ARM-mode pseudo-inst requires IsARM

2013-08-23 10:16:39 +00:00

X86

AVX-512: Added shuffle instructions -

2013-08-26 12:45:35 +00:00

XCore

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