llvm/inlineasm-sched-bug.ll at 38c6b58eec1e65c969299771a4896015151bbef7 - llvm - Gitea: Git with a cup of tea

RPCS3/llvm

mirror of https://github.com/RPCS3/llvm.git synced 2024-12-26 22:26:16 +00:00

Preston Gurd a836563e32 This patch addresses a problem with the Post RA scheduler generating an

incorrect instruction sequence due to it not being aware that an
inline assembly instruction may reference memory.

This patch fixes the problem by causing the scheduler to always assume that any
inline assembly code instruction could access memory. This is necessary because
the internal representation of the inline instruction does not include
any information about memory accesses.
 
This should fix PR13504.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166929 91177308-0d34-0410-b5e6-96231b3b80d8

2012-10-29 15:01:23 +00:00

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 ; PR13504
 ; RUN: llc -march=x86 -mcpu=atom <%s | FileCheck %s
 ; CHECK: bsfl
 ; CHECK-NOT: movl
 define i32 @foo(i32 %treemap) nounwind uwtable {
 entry:
   %sub = sub i32 0, %treemap
   %and = and i32 %treemap, %sub
   %0 = tail call i32 asm "bsfl $1,$0\0A\09", "=r,rm,~{dirflag},~{fpsr},~{flags}"(i32 %and) nounwind
   ret i32 %0
 }