llvm/test/CodeGen/X86/vec_shuffle-30.ll
Jakub Staszak a24262a0f5 Re-commit r166971. I reverted it to quickly, when buildbots didn't have a chance
to test it with chapni's fix (-mattr=+avx).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166985 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-30 00:01:57 +00:00

27 lines
881 B
LLVM

; RUN: llc < %s -march=x86 -mattr=+avx | FileCheck %s
; CHECK: test
; Test case when creating pshufhw, we incorrectly set the higher order bit
; for an undef,
define void @test(<8 x i16>* %dest, <8 x i16> %in) nounwind {
entry:
; CHECK-NOT: vmovaps
; CHECK: vmovlpd
; CHECK: vpshufhw $-95
%0 = load <8 x i16>* %dest
%1 = shufflevector <8 x i16> %0, <8 x i16> %in, <8 x i32> < i32 0, i32 1, i32 2, i32 3, i32 13, i32 undef, i32 14, i32 14>
store <8 x i16> %1, <8 x i16>* %dest
ret void
}
; CHECK: test2
; A test case where we shouldn't generate a punpckldq but a pshufd and a pslldq
define void @test2(<4 x i32>* %dest, <4 x i32> %in) nounwind {
entry:
; CHECK-NOT: pslldq
; CHECK: shufps
%0 = shufflevector <4 x i32> %in, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> < i32 undef, i32 5, i32 undef, i32 2>
store <4 x i32> %0, <4 x i32>* %dest
ret void
}