Devang Patel 394427b014 Update debug info when live-in reg is copied into a vreg. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104732 91177308-0d34-0410-b5e6-96231b3b80d8

2010-05-26 20:18:50 +00:00

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CallingConvLower.cpp

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CMakeLists.txt

Create a new TargetSelectionDAGInfo class. This will eventually acquire

2010-04-16 21:12:11 +00:00

DAGCombiner.cpp

Fix another variant of PR 7191. Also add a testcase

2010-05-25 18:47:23 +00:00

FastISel.cpp

Do one map lookup instead of two.

2010-05-25 21:59:42 +00:00

FunctionLoweringInfo.cpp

Remove the code for special-casing byval for fast-isel. SelectionDAG

2010-05-01 02:44:23 +00:00

FunctionLoweringInfo.h

Add comment.

2010-04-29 06:58:53 +00:00

InstrEmitter.cpp

Continuously refine the register class of REG_SEQUENCE def with all the source registers and sub-register indices.

2010-05-18 20:07:47 +00:00

InstrEmitter.h

Don't set kill flags for instructions which the scheduler has cloned.

2010-05-14 22:01:14 +00:00

LegalizeDAG.cpp

When expanding a vector_shuffle, the element type may not be legal and may

2010-05-19 18:48:32 +00:00

LegalizeFloatTypes.cpp

More 80 violations.

2010-04-15 01:25:27 +00:00

LegalizeIntegerTypes.cpp

Fix uint64->{float, double} conversion to do rounding correctly in 32-bit.

2010-05-15 18:51:12 +00:00

LegalizeTypes.cpp

80 col violations.

2010-04-15 01:01:55 +00:00

LegalizeTypes.h

I got tired of VISIBILITY_HIDDEN colliding with the gcc enum. Rename it

2010-05-11 20:16:09 +00:00

LegalizeTypesGeneric.cpp

More 80 violations.

2010-04-15 01:25:27 +00:00

LegalizeVectorOps.cpp

Use const qualifiers with TargetLowering. This eliminates several

2010-04-17 15:26:15 +00:00

LegalizeVectorTypes.cpp

More 80 violations.

2010-04-15 01:25:27 +00:00

Makefile

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ScheduleDAGFast.cpp

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ScheduleDAGList.cpp

Trim #include.

2010-05-26 00:55:59 +00:00

ScheduleDAGRRList.cpp

Eliminate the use of PriorityQueue and just use a std::vector,

2010-05-26 18:52:00 +00:00

ScheduleDAGSDNodes.cpp

Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.

2010-05-20 23:26:43 +00:00

ScheduleDAGSDNodes.h

Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.

2010-05-20 23:26:43 +00:00

SDNodeDbgValue.h

Add const qualifiers to CodeGen's use of LLVM IR constructs.

2010-04-15 01:51:59 +00:00

SDNodeOrdering.h

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SelectionDAG.cpp

Improve assertion messages.

2010-05-15 18:38:02 +00:00

SelectionDAGBuilder.cpp

Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit.

2010-05-22 01:06:18 +00:00

SelectionDAGBuilder.h

Don't pass SDValues by non-const reference unless they may be

2010-05-01 00:33:16 +00:00

SelectionDAGISel.cpp

Update debug info when live-in reg is copied into a vreg.

2010-05-26 20:18:50 +00:00

SelectionDAGPrinter.cpp

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TargetLowering.cpp

Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMachine.h and put it in its own namespace.

2010-05-19 20:19:50 +00:00

TargetSelectionDAGInfo.cpp

Implement a bunch more TargetSelectionDAGInfo infrastructure.

2010-05-11 17:31:57 +00:00