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0cb25a2a10
- MIParser: If the successor list is not specified successors will be added based on basic block operands in the block and possible fallthrough. - MIRPrinter: Adds a new `simplify-mir` option, with that option set: Skip printing of block successor lists in cases where the parser is guaranteed to reconstruct it. This means we still print the list if some successor cannot be determined (happens for example for jump tables), if the successor order changes or branch probabilities being unequal. Differential Revision: https://reviews.llvm.org/D31262 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302289 91177308-0d34-0410-b5e6-96231b3b80d8
31 lines
924 B
YAML
31 lines
924 B
YAML
# RUN: llc -march=amdgcn -run-pass liveintervals -verify-machineinstrs -o /dev/null -debug-only=regalloc %s 2>&1 | FileCheck %s
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# REQUIRES: asserts
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# We currently maintain a main liveness range which operates like a superset of
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# all subregister liveranges. We may need to create additional SSA values at
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# merge point in this main liverange even though none of the subregister
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# liveranges needed it.
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#
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# Should see three distinct value numbers:
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# CHECK: %vreg0 [{{.*}}:0)[{{.*}}:1)[{{.*}}:2) 0@{{[0-9]+[Berd]}} 1@{{[0-9]+[Berd]}} 2@{{[0-9]+B-phi}}
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--- |
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define amdgpu_kernel void @test0() { ret void }
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...
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---
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name: test0
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registers:
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- { id: 0, class: sreg_64 }
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body: |
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bb.0:
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S_NOP 0, implicit-def undef %0.sub0
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S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
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S_BRANCH %bb.2
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bb.1:
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S_NOP 0, implicit-def %0.sub1
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S_NOP 0, implicit %0.sub1
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S_BRANCH %bb.2
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bb.2:
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S_NOP 0, implicit %0.sub0
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...
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