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7d7873efde
Summary: This patch is the first step in reducing HW prefetcher instruction tag collisions in inner loops for Falkor. It adds a pass that annotates IR loads with metadata to indicate that they are known to be strided loads, and adds a target lowering hook that translates this metadata to a target-specific MachineMemOperand flag. A follow on change will use this MachineMemOperand flag to re-write instructions to reduce tag collisions. Reviewers: mcrosier, t.p.northover Subscribers: aemerson, rengolin, mgorny, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D34963 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308059 91177308-0d34-0410-b5e6-96231b3b80d8
27 lines
835 B
YAML
27 lines
835 B
YAML
# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass none -o - %s | FileCheck %s
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--- |
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define void @target_memoperands() {
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ret void
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}
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...
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---
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# CHECK-LABEL: name: target_memoperands
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# CHECK: %1(s64) = G_LOAD %0(p0) :: ("aarch64-suppress-pair" load 8)
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# CHECK: %2(s32) = G_LOAD %0(p0) :: ("aarch64-strided-access" load 4)
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# CHECK: G_STORE %1(s64), %0(p0) :: ("aarch64-suppress-pair" store 8)
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# CHECK: G_STORE %2(s32), %0(p0) :: ("aarch64-strided-access" store 4)
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name: target_memoperands
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body: |
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bb.0:
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%0:_(p0) = COPY %x0
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%1:_(s64) = G_LOAD %0(p0) :: ("aarch64-suppress-pair" load 8)
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%2:_(s32) = G_LOAD %0(p0) :: ("aarch64-strided-access" load 4)
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G_STORE %1(s64), %0(p0) :: ("aarch64-suppress-pair" store 8)
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G_STORE %2(s32), %0(p0) :: ("aarch64-strided-access" store 4)
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RET_ReallyLR
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...
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