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3ed469ccd7
Turn on -Wunused and -Wno-unused-parameter. Clean up most of the resulting fall out by removing unused variables. Remaining warnings have to do with unused functions (I didn't want to delete code without review) and unused variables in generated code. Maintainers should clean up the remaining issues when they see them. All changes pass DejaGnu tests and Olden. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31380 91177308-0d34-0410-b5e6-96231b3b80d8
227 lines
7.3 KiB
C++
227 lines
7.3 KiB
C++
//===-- Alpha/AlphaCodeEmitter.cpp - Convert Alpha code to machine code ---===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the pass that transforms the Alpha machine instructions
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// into relocatable machine code.
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//
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//===----------------------------------------------------------------------===//
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#include "AlphaTargetMachine.h"
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#include "AlphaRelocations.h"
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#include "Alpha.h"
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#include "llvm/PassManager.h"
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#include "llvm/CodeGen/MachineCodeEmitter.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Function.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/ADT/Statistic.h"
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#include <iostream>
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using namespace llvm;
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namespace {
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Statistic<>
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NumEmitted("alpha-emitter", "Number of machine instructions emitted");
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}
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namespace {
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class AlphaCodeEmitter : public MachineFunctionPass {
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const AlphaInstrInfo *II;
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TargetMachine &TM;
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MachineCodeEmitter &MCE;
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/// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr
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///
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int getMachineOpValue(MachineInstr &MI, MachineOperand &MO);
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public:
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explicit AlphaCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce)
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: II(0), TM(tm), MCE(mce) {}
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AlphaCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce,
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const AlphaInstrInfo& ii)
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: II(&ii), TM(tm), MCE(mce) {}
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bool runOnMachineFunction(MachineFunction &MF);
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virtual const char *getPassName() const {
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return "Alpha Machine Code Emitter";
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}
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void emitInstruction(const MachineInstr &MI);
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/// getBinaryCodeForInstr - This function, generated by the
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/// CodeEmitterGenerator using TableGen, produces the binary encoding for
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/// machine instructions.
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///
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unsigned getBinaryCodeForInstr(MachineInstr &MI);
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private:
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void emitBasicBlock(MachineBasicBlock &MBB);
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};
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}
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/// createAlphaCodeEmitterPass - Return a pass that emits the collected Alpha code
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/// to the specified MCE object.
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FunctionPass *llvm::createAlphaCodeEmitterPass(AlphaTargetMachine &TM,
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MachineCodeEmitter &MCE) {
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return new AlphaCodeEmitter(TM, MCE);
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}
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bool AlphaCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
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II = ((AlphaTargetMachine&)MF.getTarget()).getInstrInfo();
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do {
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MCE.startFunction(MF);
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for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
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emitBasicBlock(*I);
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} while (MCE.finishFunction(MF));
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return false;
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}
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void AlphaCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
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MCE.StartMachineBasicBlock(&MBB);
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for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
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I != E; ++I) {
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MachineInstr &MI = *I;
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switch(MI.getOpcode()) {
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default:
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MCE.emitWordLE(getBinaryCodeForInstr(*I));
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break;
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case Alpha::ALTENT:
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case Alpha::PCLABEL:
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case Alpha::MEMLABEL:
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case Alpha::IDEF_I:
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case Alpha::IDEF_F32:
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case Alpha::IDEF_F64:
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break; //skip these
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}
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}
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}
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static unsigned getAlphaRegNumber(unsigned Reg) {
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switch (Reg) {
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case Alpha::R0 : case Alpha::F0 : return 0;
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case Alpha::R1 : case Alpha::F1 : return 1;
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case Alpha::R2 : case Alpha::F2 : return 2;
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case Alpha::R3 : case Alpha::F3 : return 3;
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case Alpha::R4 : case Alpha::F4 : return 4;
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case Alpha::R5 : case Alpha::F5 : return 5;
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case Alpha::R6 : case Alpha::F6 : return 6;
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case Alpha::R7 : case Alpha::F7 : return 7;
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case Alpha::R8 : case Alpha::F8 : return 8;
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case Alpha::R9 : case Alpha::F9 : return 9;
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case Alpha::R10 : case Alpha::F10 : return 10;
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case Alpha::R11 : case Alpha::F11 : return 11;
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case Alpha::R12 : case Alpha::F12 : return 12;
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case Alpha::R13 : case Alpha::F13 : return 13;
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case Alpha::R14 : case Alpha::F14 : return 14;
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case Alpha::R15 : case Alpha::F15 : return 15;
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case Alpha::R16 : case Alpha::F16 : return 16;
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case Alpha::R17 : case Alpha::F17 : return 17;
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case Alpha::R18 : case Alpha::F18 : return 18;
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case Alpha::R19 : case Alpha::F19 : return 19;
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case Alpha::R20 : case Alpha::F20 : return 20;
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case Alpha::R21 : case Alpha::F21 : return 21;
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case Alpha::R22 : case Alpha::F22 : return 22;
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case Alpha::R23 : case Alpha::F23 : return 23;
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case Alpha::R24 : case Alpha::F24 : return 24;
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case Alpha::R25 : case Alpha::F25 : return 25;
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case Alpha::R26 : case Alpha::F26 : return 26;
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case Alpha::R27 : case Alpha::F27 : return 27;
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case Alpha::R28 : case Alpha::F28 : return 28;
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case Alpha::R29 : case Alpha::F29 : return 29;
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case Alpha::R30 : case Alpha::F30 : return 30;
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case Alpha::R31 : case Alpha::F31 : return 31;
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default:
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assert(0 && "Unhandled reg");
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abort();
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}
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}
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int AlphaCodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
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int rv = 0; // Return value; defaults to 0 for unhandled cases
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// or things that get fixed up later by the JIT.
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if (MO.isRegister()) {
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rv = getAlphaRegNumber(MO.getReg());
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} else if (MO.isImmediate()) {
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rv = MO.getImmedValue();
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} else if (MO.isGlobalAddress() || MO.isExternalSymbol()
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|| MO.isConstantPoolIndex()) {
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DEBUG(std::cerr << MO << " is a relocated op for " << MI << "\n";);
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unsigned Reloc = 0;
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int Offset = 0;
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bool useGOT = false;
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switch (MI.getOpcode()) {
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case Alpha::BSR:
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Reloc = Alpha::reloc_bsr;
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break;
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case Alpha::LDLr:
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case Alpha::LDQr:
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case Alpha::LDBUr:
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case Alpha::LDWUr:
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case Alpha::LDSr:
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case Alpha::LDTr:
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case Alpha::LDAr:
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case Alpha::STQr:
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case Alpha::STLr:
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case Alpha::STWr:
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case Alpha::STBr:
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case Alpha::STSr:
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case Alpha::STTr:
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Reloc = Alpha::reloc_gprellow;
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break;
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case Alpha::LDAHr:
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Reloc = Alpha::reloc_gprelhigh;
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break;
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case Alpha::LDQl:
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Reloc = Alpha::reloc_literal;
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useGOT = true;
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break;
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case Alpha::LDAg:
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case Alpha::LDAHg:
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Reloc = Alpha::reloc_gpdist;
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Offset = MI.getOperand(3).getImmedValue();
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break;
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default:
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assert(0 && "unknown relocatable instruction");
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abort();
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}
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if (MO.isGlobalAddress())
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MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
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Reloc, MO.getGlobal(), Offset,
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false, useGOT));
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else if (MO.isExternalSymbol())
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MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
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Reloc, MO.getSymbolName(), Offset,
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true));
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else
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MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
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Reloc, MO.getConstantPoolIndex(),
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Offset));
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} else if (MO.isMachineBasicBlock()) {
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MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
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Alpha::reloc_bsr,
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MO.getMachineBasicBlock()));
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}else {
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std::cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
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abort();
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}
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return rv;
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}
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#include "AlphaGenCodeEmitter.inc"
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