Sanjay Patel 3f985a3da1 [TargetLowering] try to create -1 constant operand for math ops via demanded bits ...

This reverses instcombine's demanded bits' transform which always tries to clear bits in constants.

As noted in PR35792 and shown in the test diffs:
https://bugs.llvm.org/show_bug.cgi?id=35792
...we can do better in codegen by trying to form -1. The x86 sub test shows a missed opportunity. 

I did investigate changing instcombine's behavior, but it would be more work to change 
canonicalization in IR. Clearing bits / shrinking constants can allow killing instructions, 
so we'd have to figure out how to not regress those cases.

Differential Revision: https://reviews.llvm.org/D42986


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324839 91177308-0d34-0410-b5e6-96231b3b80d8

2018-02-11 14:38:23 +00:00

..

AArch64

[TargetLowering] try to create -1 constant operand for math ops via demanded bits

2018-02-11 14:38:23 +00:00

AMDGPU

Reapply "AMDGPU: Add 32-bit constant address space"

2018-02-09 16:57:57 +00:00

ARC

[ARC] Add ARC backend.

2017-08-24 15:40:33 +00:00

ARM

[ARM] preserve test intent by removing undef

2018-02-10 15:14:00 +00:00

AVR

[CodeGen] Unify the syntax of MBB successors in MIR and -debug output

2018-02-09 00:10:31 +00:00

BPF

bpf: Improve expanding logic in LowerSELECT_CC

2018-02-08 04:37:49 +00:00

Generic

[CodeGen] Unify the syntax of MBB successors in MIR and -debug output

2018-02-09 00:10:31 +00:00

Hexagon

[Hexagon] Add code to select QTRUE and QFALSE

2018-02-09 19:10:46 +00:00

Inputs

…

Lanai

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

Mips

[DebugInfo] Don't insert DEBUG_VALUE after terminators

2018-02-09 14:03:26 +00:00

MIR

[GISel]: Verify COPIES involving generic registers.

2018-02-09 01:27:23 +00:00

MSP430

Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)

2018-01-19 17:13:12 +00:00

Nios2

[Nios2] Arithmetic instructions for R1 and R2 ISA.

2018-01-09 11:15:08 +00:00

NVPTX

Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)

2018-01-19 17:13:12 +00:00

PowerPC

[MergeICmps] Re-commit rL324317 "Enable the MergeICmps Pass by default."

2018-02-07 09:58:55 +00:00

RISCV

[RISCV] Update two RISCV codegen tests after rL323991

2018-02-03 13:02:30 +00:00

SPARC

[MachineCopyPropagation] Extend pass to do COPY source forwarding

2018-02-01 18:54:01 +00:00

SystemZ

[SelectionDAG] Consider endianness in scalarizeVectorStore().

2018-02-02 08:48:02 +00:00

Thumb

[LivePhysRegs] Fix handling of return instructions.

2018-02-06 23:00:17 +00:00

Thumb2

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

WebAssembly

[WebAssembly] Add mechanisms for specifying an explicit import module name.

2018-02-09 23:13:22 +00:00

WinCFGuard

Reland "Emit Function IDs table for Control Flow Guard"

2018-01-09 23:49:30 +00:00

WinEH

Make x86 __ehhandler comdat if parent function is

2017-10-20 17:04:43 +00:00

X86

[TargetLowering] try to create -1 constant operand for math ops via demanded bits

2018-02-11 14:38:23 +00:00

XCore

Emit smaller exception tables for non-SJLJ mode.

2018-02-09 17:13:37 +00:00