mirror of
https://github.com/RPCS3/llvm.git
synced 2024-12-26 14:15:53 +00:00
aa6ec15caf
SGPRs are spilled into VGPRs using the {READ,WRITE}LANE_B32 instructions.
v2:
- Fix encoding of Lane Mask
- Use correct register flags, so we don't overwrite the low dword
when restoring multi-dword registers.
v3:
- Register spilling seems to hang the GPU, so replace all shaders
that need spilling with a dummy shader.
v4:
- Fix *LANE definitions
- Change destination reg class for 32-bit SMRD instructions
v5:
- Remove small optimization that was crashing Serious Sam 3.
https://bugs.freedesktop.org/show_bug.cgi?id=68224
https://bugs.freedesktop.org/show_bug.cgi?id=71285
NOTE: This is a candidate for the 3.4 branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195880 91177308-0d34-0410-b5e6-96231b3b80d8
56 lines
1.6 KiB
C++
56 lines
1.6 KiB
C++
//===-- SIMachineFunctionInfo.cpp - SI Machine Function Info -------===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
/// \file
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
#include "SIMachineFunctionInfo.h"
|
|
#include "SIRegisterInfo.h"
|
|
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
|
|
|
#define MAX_LANES 64
|
|
|
|
using namespace llvm;
|
|
|
|
|
|
// Pin the vtable to this file.
|
|
void SIMachineFunctionInfo::anchor() {}
|
|
|
|
SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
|
|
: AMDGPUMachineFunction(MF),
|
|
PSInputAddr(0),
|
|
SpillTracker() { }
|
|
|
|
static unsigned createLaneVGPR(MachineRegisterInfo &MRI) {
|
|
return MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
|
|
}
|
|
|
|
unsigned SIMachineFunctionInfo::RegSpillTracker::getNextLane(MachineRegisterInfo &MRI) {
|
|
if (!LaneVGPR) {
|
|
LaneVGPR = createLaneVGPR(MRI);
|
|
} else {
|
|
CurrentLane++;
|
|
if (CurrentLane == MAX_LANES) {
|
|
CurrentLane = 0;
|
|
LaneVGPR = createLaneVGPR(MRI);
|
|
}
|
|
}
|
|
return CurrentLane;
|
|
}
|
|
|
|
void SIMachineFunctionInfo::RegSpillTracker::addSpilledReg(unsigned FrameIndex,
|
|
unsigned Reg,
|
|
int Lane) {
|
|
SpilledRegisters[FrameIndex] = SpilledReg(Reg, Lane);
|
|
}
|
|
|
|
const SIMachineFunctionInfo::SpilledReg&
|
|
SIMachineFunctionInfo::RegSpillTracker::getSpilledReg(unsigned FrameIndex) {
|
|
return SpilledRegisters[FrameIndex];
|
|
}
|