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https://github.com/RPCS3/llvm.git
synced 2026-07-19 15:13:49 -04:00
Anton Korobeynikov
695940b0f1
Reapply r346374 with the fixes for modules build. Original summary: This change implements assembler parser, code emitter, ELF object writer and disassembler for the MSP430 ISA. Also, more instruction forms are added to the target description. Patch by Michael Skvortsov! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346948 91177308-0d34-0410-b5e6-96231b3b80d8
75 lines
1.6 KiB
LLVM
75 lines
1.6 KiB
LLVM
; RUN: llc < %s -march=msp430 | FileCheck %s
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target datalayout = "e-p:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:16:16"
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target triple = "msp430-generic-generic"
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define i16 @am1(i16 %x, i16* %a) nounwind {
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%1 = load i16, i16* %a
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%2 = or i16 %1,%x
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ret i16 %2
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}
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; CHECK-LABEL: am1:
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; CHECK: bis 0(r13), r12
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@foo = external global i16
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define i16 @am2(i16 %x) nounwind {
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%1 = load i16, i16* @foo
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%2 = or i16 %1,%x
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ret i16 %2
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}
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; CHECK-LABEL: am2:
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; CHECK: bis &foo, r12
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@bar = internal constant [2 x i8] [ i8 32, i8 64 ]
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define i8 @am3(i8 %x, i16 %n) nounwind {
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%1 = getelementptr [2 x i8], [2 x i8]* @bar, i16 0, i16 %n
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%2 = load i8, i8* %1
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%3 = or i8 %2,%x
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ret i8 %3
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}
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; CHECK-LABEL: am3:
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; CHECK: bis.b bar(r13), r12
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define i16 @am4(i16 %x) nounwind {
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%1 = load volatile i16, i16* inttoptr(i16 32 to i16*)
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%2 = or i16 %1,%x
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ret i16 %2
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}
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; CHECK-LABEL: am4:
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; CHECK: bis &32, r12
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define i16 @am5(i16 %x, i16* %a) nounwind {
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%1 = getelementptr i16, i16* %a, i16 2
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%2 = load i16, i16* %1
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%3 = or i16 %2,%x
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ret i16 %3
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}
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; CHECK-LABEL: am5:
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; CHECK: bis 4(r13), r12
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%S = type { i16, i16 }
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@baz = common global %S zeroinitializer, align 1
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define i16 @am6(i16 %x) nounwind {
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%1 = load i16, i16* getelementptr (%S, %S* @baz, i32 0, i32 1)
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%2 = or i16 %1,%x
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ret i16 %2
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}
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; CHECK-LABEL: am6:
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; CHECK: bis &baz+2, r12
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%T = type { i16, [2 x i8] }
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@duh = internal constant %T { i16 16, [2 x i8][i8 32, i8 64 ] }
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define i8 @am7(i8 %x, i16 %n) nounwind {
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%1 = getelementptr %T, %T* @duh, i32 0, i32 1
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%2 = getelementptr [2 x i8], [2 x i8]* %1, i16 0, i16 %n
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%3= load i8, i8* %2
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%4 = or i8 %3,%x
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ret i8 %4
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}
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; CHECK-LABEL: am7:
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; CHECK: bis.b duh+2(r13), r12
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