llvm/lib/CodeGen
Francis Visoiu Mistrih ee30ab7184 [CodeGen] Print MCSymbol operands as <mcsymbol sym> in both MIR and debug output
Work towards the unification of MIR and debug output by printing
`<mcsymbol sym>` instead of `<MCSym=sym>`.

Only debug syntax is affected.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320685 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 10:03:23 +00:00
..
AsmPrinter MC/AsmPrinter: Reduce code duplication. 2017-12-14 03:59:24 +00:00
GlobalISel Remove redundant includes from lib/CodeGen. 2017-12-13 21:30:47 +00:00
MIRParser Remove redundant includes from lib/CodeGen. 2017-12-13 21:30:47 +00:00
SelectionDAG [DAGCombine] Move AND nodes to multiple load leaves 2017-12-14 09:31:01 +00:00
AggressiveAntiDepBreaker.cpp [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register. 2017-12-07 10:40:31 +00:00
AggressiveAntiDepBreaker.h Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
AllocationOrder.cpp [CodeGen] Rename functions PrintReg* to printReg* 2017-11-28 12:42:37 +00:00
AllocationOrder.h [RegAlloc, SystemZ] Increase number of LOCRs by passing "hard" regalloc hints. 2017-11-10 08:46:26 +00:00
Analysis.cpp Remove redundant includes from lib/CodeGen. 2017-12-13 21:30:47 +00:00
AntiDepBreaker.h
AtomicExpandPass.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
BasicTargetTransformInfo.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
BranchFolding.cpp [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register. 2017-12-07 10:40:31 +00:00
BranchFolding.h
BranchRelaxation.cpp [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
BuiltinGCs.cpp
CalcSpillWeights.cpp Rename LiveIntervalAnalysis.h to LiveIntervals.h 2017-12-13 02:51:04 +00:00
CallingConvLower.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
CMakeLists.txt Rename LiveIntervalAnalysis.h to LiveIntervals.h 2017-12-13 02:51:04 +00:00
CodeGen.cpp Rename CountingFunctionInserter and use for both mcount and cygprofile calls, before and after inlining 2017-11-14 21:09:45 +00:00
CodeGenPrepare.cpp Revert "[CGP] Enable select in complex addr mode" 2017-12-13 07:39:35 +00:00
CriticalAntiDepBreaker.cpp [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register. 2017-12-07 10:40:31 +00:00
CriticalAntiDepBreaker.h
DeadMachineInstructionElim.cpp Remove redundant includes from lib/CodeGen. 2017-12-13 21:30:47 +00:00
DetectDeadLanes.cpp Remove redundant includes from lib/CodeGen. 2017-12-13 21:30:47 +00:00
DFAPacketizer.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
DwarfEHPrepare.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
EarlyIfConversion.cpp [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
EdgeBundles.cpp [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
ExecutionDepsFix.cpp [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
ExpandISelPseudos.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
ExpandMemCmp.cpp Remove redundant includes from lib/CodeGen. 2017-12-13 21:30:47 +00:00
ExpandPostRAPseudos.cpp [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register. 2017-12-07 10:40:31 +00:00
ExpandReductions.cpp
FaultMaps.cpp
FEntryInserter.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
FuncletLayout.cpp
GCMetadata.cpp
GCMetadataPrinter.cpp
GCRootLowering.cpp Remove redundant includes from lib/CodeGen. 2017-12-13 21:30:47 +00:00
GCStrategy.cpp
GlobalMerge.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
IfConversion.cpp [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
ImplicitNullChecks.cpp [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register. 2017-12-07 10:40:31 +00:00
InlineSpiller.cpp Rename LiveIntervalAnalysis.h to LiveIntervals.h 2017-12-13 02:51:04 +00:00
InterferenceCache.cpp Rename LiveIntervalAnalysis.h to LiveIntervals.h 2017-12-13 02:51:04 +00:00
InterferenceCache.h
InterleavedAccessPass.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
IntrinsicLowering.cpp Support generic lowering of vector bswap 2017-11-30 11:06:22 +00:00
LatencyPriorityQueue.cpp Assert correct removal of SUnit in LatencyPriorityQueue 2017-11-16 10:18:07 +00:00
LazyMachineBlockFrequencyInfo.cpp
LexicalScopes.cpp
LiveDebugValues.cpp Remove redundant includes from lib/CodeGen. 2017-12-13 21:30:47 +00:00
LiveDebugVariables.cpp Rename LiveIntervalAnalysis.h to LiveIntervals.h 2017-12-13 02:51:04 +00:00
LiveDebugVariables.h
LiveInterval.cpp Rename LiveIntervalAnalysis.h to LiveIntervals.h 2017-12-13 02:51:04 +00:00
LiveIntervals.cpp Rename LiveIntervalAnalysis.h to LiveIntervals.h 2017-12-13 02:51:04 +00:00
LiveIntervalUnion.cpp [CodeGen] Rename functions PrintReg* to printReg* 2017-11-28 12:42:37 +00:00
LivePhysRegs.cpp [CodeGen] Rename functions PrintReg* to printReg* 2017-11-28 12:42:37 +00:00
LiveRangeCalc.cpp Rename LiveIntervalAnalysis.h to LiveIntervals.h 2017-12-13 02:51:04 +00:00
LiveRangeCalc.h
LiveRangeEdit.cpp Rename LiveIntervalAnalysis.h to LiveIntervals.h 2017-12-13 02:51:04 +00:00
LiveRangeShrink.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
LiveRangeUtils.h
LiveRegMatrix.cpp Rename LiveIntervalAnalysis.h to LiveIntervals.h 2017-12-13 02:51:04 +00:00
LiveRegUnits.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
LiveStackAnalysis.cpp Rename LiveIntervalAnalysis.h to LiveIntervals.h 2017-12-13 02:51:04 +00:00
LiveVariables.cpp Remove redundant includes from lib/CodeGen. 2017-12-13 21:30:47 +00:00
LLVMBuild.txt
LLVMTargetMachine.cpp Remove redundant includes from lib/CodeGen. 2017-12-13 21:30:47 +00:00
LocalStackSlotAllocation.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
LowerEmuTLS.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
LowLevelType.cpp
MachineBasicBlock.cpp Rename LiveIntervalAnalysis.h to LiveIntervals.h 2017-12-13 02:51:04 +00:00
MachineBlockFrequencyInfo.cpp
MachineBlockPlacement.cpp [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
MachineBranchProbabilityInfo.cpp [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
MachineCombiner.cpp Remove redundant includes from lib/CodeGen. 2017-12-13 21:30:47 +00:00
MachineCopyPropagation.cpp Remove redundant includes from lib/CodeGen. 2017-12-13 21:30:47 +00:00
MachineCSE.cpp [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register. 2017-12-07 10:40:31 +00:00
MachineDominanceFrontier.cpp
MachineDominators.cpp [[Machine]Dominators] Improved printout when verifyDomTree fails [NFC] 2017-12-06 09:27:48 +00:00
MachineFrameInfo.cpp MachineFrameInfo: Cleanup some parameter naming inconsistencies; NFC 2017-12-05 01:18:15 +00:00
MachineFunction.cpp [CodeGen] Print jump-table index operands as %jump-table.0 in both MIR and debug output 2017-12-13 10:30:59 +00:00
MachineFunctionPass.cpp
MachineFunctionPrinterPass.cpp
MachineInstr.cpp [CodeGen] Move printing MO_Immediate operands to MachineOperand::print 2017-12-08 22:53:21 +00:00
MachineInstrBundle.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
MachineLICM.cpp [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
MachineLoopInfo.cpp
MachineModuleInfo.cpp Remove redundant includes from lib/CodeGen. 2017-12-13 21:30:47 +00:00
MachineModuleInfoImpls.cpp
MachineOperand.cpp [CodeGen] Print MCSymbol operands as <mcsymbol sym> in both MIR and debug output 2017-12-14 10:03:23 +00:00
MachineOptimizationRemarkEmitter.cpp Remove redundant includes from lib/CodeGen. 2017-12-13 21:30:47 +00:00
MachineOutliner.cpp Remove redundant includes from lib/CodeGen. 2017-12-13 21:30:47 +00:00
MachinePassRegistry.cpp
MachinePipeliner.cpp Rename LiveIntervalAnalysis.h to LiveIntervals.h 2017-12-13 02:51:04 +00:00
MachinePostDominators.cpp
MachineRegionInfo.cpp
MachineRegisterInfo.cpp [CodeGen] Rename functions PrintReg* to printReg* 2017-11-28 12:42:37 +00:00
MachineScheduler.cpp CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.value 2017-12-13 22:38:09 +00:00
MachineSink.cpp Fix out-of-order stepping behavior in programs with sunk instructions. 2017-12-09 00:17:01 +00:00
MachineSSAUpdater.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
MachineTraceMetrics.cpp [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
MachineVerifier.cpp Rename LiveIntervalAnalysis.h to LiveIntervals.h 2017-12-13 02:51:04 +00:00
MacroFusion.cpp [CodeGen] Improve the consistency of instruction fusion* 2017-12-11 21:09:27 +00:00
MIRCanonicalizerPass.cpp Remove redundant includes from lib/CodeGen. 2017-12-13 21:30:47 +00:00
MIRPrinter.cpp [CodeGen] Print MCSymbol operands as <mcsymbol sym> in both MIR and debug output 2017-12-14 10:03:23 +00:00
MIRPrintingPass.cpp Remove redundant includes from lib/CodeGen. 2017-12-13 21:30:47 +00:00
OptimizePHIs.cpp Remove redundant includes from lib/CodeGen. 2017-12-13 21:30:47 +00:00
ParallelCG.cpp Remove redundant includes from lib/CodeGen. 2017-12-13 21:30:47 +00:00
PatchableFunction.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
PeepholeOptimizer.cpp [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output 2017-11-30 12:12:19 +00:00
PHIElimination.cpp Rename LiveIntervalAnalysis.h to LiveIntervals.h 2017-12-13 02:51:04 +00:00
PHIEliminationUtils.cpp
PHIEliminationUtils.h
PostRAHazardRecognizer.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
PostRASchedulerList.cpp Remove redundant includes from lib/CodeGen. 2017-12-13 21:30:47 +00:00
PreISelIntrinsicLowering.cpp
ProcessImplicitDefs.cpp [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
PrologEpilogInserter.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
PseudoSourceValue.cpp Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering 2017-11-08 01:01:31 +00:00
README.txt [CodeGen] Print register names in lowercase in both MIR and debug output 2017-11-28 17:15:09 +00:00
RegAllocBase.cpp Rename LiveIntervalAnalysis.h to LiveIntervals.h 2017-12-13 02:51:04 +00:00
RegAllocBase.h
RegAllocBasic.cpp Rename LiveIntervalAnalysis.h to LiveIntervals.h 2017-12-13 02:51:04 +00:00
RegAllocFast.cpp Remove redundant includes from lib/CodeGen. 2017-12-13 21:30:47 +00:00
RegAllocGreedy.cpp Rename LiveIntervalAnalysis.h to LiveIntervals.h 2017-12-13 02:51:04 +00:00
RegAllocPBQP.cpp Rename LiveIntervalAnalysis.h to LiveIntervals.h 2017-12-13 02:51:04 +00:00
RegisterClassInfo.cpp [CodeGen] Rename functions PrintReg* to printReg* 2017-11-28 12:42:37 +00:00
RegisterCoalescer.cpp Rename LiveIntervalAnalysis.h to LiveIntervals.h 2017-12-13 02:51:04 +00:00
RegisterCoalescer.h
RegisterPressure.cpp Rename LiveIntervalAnalysis.h to LiveIntervals.h 2017-12-13 02:51:04 +00:00
RegisterScavenging.cpp [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register. 2017-12-07 10:40:31 +00:00
RegisterUsageInfo.cpp [CodeGen] Always use printReg to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
RegUsageInfoCollector.cpp [CodeGen] Always use printReg to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
RegUsageInfoPropagate.cpp
RenameIndependentSubregs.cpp Rename LiveIntervalAnalysis.h to LiveIntervals.h 2017-12-13 02:51:04 +00:00
ResetMachineFunctionPass.cpp
SafeStack.cpp Generalize llvm::replaceDbgDeclare and actually support the use-case that 2017-12-08 21:58:18 +00:00
SafeStackColoring.cpp
SafeStackColoring.h
SafeStackLayout.cpp
SafeStackLayout.h
ScalarizeMaskedMemIntrin.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
ScheduleDAG.cpp [CodeGen] Rename functions PrintReg* to printReg* 2017-11-28 12:42:37 +00:00
ScheduleDAGInstrs.cpp CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.value 2017-12-13 22:38:09 +00:00
ScheduleDAGPrinter.cpp Remove redundant includes from lib/CodeGen. 2017-12-13 21:30:47 +00:00
ScoreboardHazardRecognizer.cpp Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering 2017-11-08 01:01:31 +00:00
ShadowStackGCLowering.cpp
ShrinkWrap.cpp Ignore metainstructions during the shrink wrap analysis 2017-12-13 19:10:54 +00:00
SjLjEHPrepare.cpp
SlotIndexes.cpp Remove redundant includes from lib/CodeGen. 2017-12-13 21:30:47 +00:00
Spiller.h
SpillPlacement.cpp
SpillPlacement.h
SplitKit.cpp Rename LiveIntervalAnalysis.h to LiveIntervals.h 2017-12-13 02:51:04 +00:00
SplitKit.h
StackColoring.cpp [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
StackMapLivenessAnalysis.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
StackMaps.cpp Mark all library options as hidden. 2017-12-01 00:53:10 +00:00
StackProtector.cpp Re-commit r319490 "XOR the frame pointer with the stack cookie when protecting the stack" 2017-12-05 20:22:20 +00:00
StackSlotColoring.cpp Rename LiveIntervalAnalysis.h to LiveIntervals.h 2017-12-13 02:51:04 +00:00
TailDuplication.cpp Remove unnecessary includes; NFC 2017-12-13 02:51:01 +00:00
TailDuplicator.cpp [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
TargetFrameLoweringImpl.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
TargetInstrInfo.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
TargetLoweringBase.cpp Relax unaligned access assertion when type is byte aligned 2017-12-09 06:45:36 +00:00
TargetLoweringObjectFileImpl.cpp [WebAssembly] section kind can be code 2017-12-07 02:55:51 +00:00
TargetOptionsImpl.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
TargetPassConfig.cpp Mark all library options as hidden. 2017-12-01 00:53:10 +00:00
TargetRegisterInfo.cpp [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register. 2017-12-07 10:40:31 +00:00
TargetSchedule.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
TargetSubtargetInfo.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
TwoAddressInstructionPass.cpp Rename LiveIntervalAnalysis.h to LiveIntervals.h 2017-12-13 02:51:04 +00:00
UnreachableBlockElim.cpp Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering 2017-11-08 01:01:31 +00:00
VirtRegMap.cpp Rename LiveIntervalAnalysis.h to LiveIntervals.h 2017-12-13 02:51:04 +00:00
WinEHPrepare.cpp
XRayInstrumentation.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str r4, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelihood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %noreg, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvements:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.