Evan Cheng 46dcb57e18 Teach computeRegisterProperties() to compute "representative" register class for legal value types. A "representative" register class is the largest legal super-reg register class for a value type. e.g. On i386, GR32 is the rep register class for i8 / i16 / i32; on x86_64 it would be GR64. ...

This property will be used by the register pressure tracking instruction scheduler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108735 91177308-0d34-0410-b5e6-96231b3b80d8

2010-07-19 18:47:01 +00:00

..

CMakeLists.txt

Move CallingConvLower.cpp out of the SelectionDAG directory.

2010-07-07 15:15:27 +00:00

DAGCombiner.cpp

Remove r108639 now that it is handled by InstCombine instead.

2010-07-19 08:10:24 +00:00

FastISel.cpp

Revert r108369, sorting llvm.dbg.declare information by source position,

2010-07-16 17:54:27 +00:00

FunctionLoweringInfo.cpp

Revert r108369, sorting llvm.dbg.declare information by source position,

2010-07-16 17:54:27 +00:00

InstrEmitter.cpp

Emit COPY instructions instead of using copyRegToReg in InstrEmitter,

2010-07-10 19:08:25 +00:00

InstrEmitter.h

Don't set kill flags for instructions which the scheduler has cloned.

2010-05-14 22:01:14 +00:00

LegalizeDAG.cpp

Fix va_arg for doubles. With this patch VAARG nodes always contain the

2010-07-11 04:01:49 +00:00

LegalizeFloatTypes.cpp

Convert some tab stops into spaces.

2010-07-12 08:16:59 +00:00

LegalizeIntegerTypes.cpp

Fix va_arg for doubles. With this patch VAARG nodes always contain the

2010-07-11 04:01:49 +00:00

LegalizeTypes.cpp

Use A.append(...) instead of A.insert(A.end(), ...) when A is a

2010-06-21 19:47:52 +00:00

LegalizeTypes.h

Implement expansion in type legalization for add/sub with overflow. The

2010-06-03 03:49:50 +00:00

LegalizeTypesGeneric.cpp

Fix va_arg for doubles. With this patch VAARG nodes always contain the

2010-07-11 04:01:49 +00:00

LegalizeVectorOps.cpp

Change UpdateNodeOperands' operand and return value from SDValue to

2010-06-18 15:30:29 +00:00

LegalizeVectorTypes.cpp

Move getExtLoad() and (some) getLoad() DebugLoc argument after EVT argument for consistency sake.

2010-07-07 22:15:37 +00:00

Makefile

make -fno-rtti the default unless a directory builds with REQUIRES_RTTI.

2010-01-24 20:43:08 +00:00

ScheduleDAGFast.cpp

Add a VT argument to getMinimalPhysRegClass and replace the copy related uses

2010-06-29 14:02:34 +00:00

ScheduleDAGList.cpp

Trim #include.

2010-05-26 00:55:59 +00:00

ScheduleDAGRRList.cpp

Add a VT argument to getMinimalPhysRegClass and replace the copy related uses

2010-06-29 14:02:34 +00:00

ScheduleDAGSDNodes.cpp

Fix a bug in the code which re-inserts DBG_VALUE nodes after scheduling;

2010-07-10 22:42:31 +00:00

ScheduleDAGSDNodes.h

Code refactoring, no functionality changes.

2010-06-10 02:09:31 +00:00

SDNodeDbgValue.h

Add const qualifiers to CodeGen's use of LLVM IR constructs.

2010-04-15 01:51:59 +00:00

SDNodeOrdering.h

Allow 0 as an order number. Don't assign an order to formal arguments.

2009-12-22 21:35:02 +00:00

SelectionDAG.cpp

Split -enable-finite-only-fp-math to two options:

2010-07-15 22:07:12 +00:00

SelectionDAGBuilder.cpp

Propagate alloca alignment information via variable size object frame

2010-07-17 00:28:22 +00:00

SelectionDAGBuilder.h

The SelectionDAGBuilder's handling of debug info, on rare

2010-07-16 00:02:08 +00:00

SelectionDAGISel.cpp

Use the source-order scheduler instead of the "fast" scheduler at -O0,

2010-07-16 02:01:19 +00:00

SelectionDAGPrinter.cpp

Convert some tab stops into spaces.

2010-07-12 08:16:59 +00:00

TargetLowering.cpp

Teach computeRegisterProperties() to compute "representative" register class for legal value types. A "representative" register class is the largest legal super-reg register class for a value type. e.g. On i386, GR32 is the rep register class for i8 / i16 / i32; on x86_64 it would be GR64.

2010-07-19 18:47:01 +00:00

TargetSelectionDAGInfo.cpp

Implement a bunch more TargetSelectionDAGInfo infrastructure.

2010-05-11 17:31:57 +00:00