Sanjoy Das 477137f4d7 [LSR] Generate and use zero extends ...

Summary:
If a scale or a base register can be rewritten as "Zext({A,+,1})" then
LSR will now consider a formula of that form in its normal cost
computation.

Depends on D9180

Reviewers: qcolombet, atrick

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9181

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243348 91177308-0d34-0410-b5e6-96231b3b80d8

2015-07-27 23:27:51 +00:00

..

Analysis

[TargetTransformInfo][NFCI] Add TargetTransformInfo::isZExtFree.

2015-07-27 23:27:43 +00:00

AsmParser

AsmParser: Add a function to parse a standalone constant value.

2015-07-17 22:07:03 +00:00

Bitcode

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CodeGen

MIR Serialization: Serialize the unnamed basic block references.

2015-07-27 22:42:41 +00:00

DebugInfo

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ExecutionEngine

Fix ODR violation. NFC.

2015-07-27 18:27:23 +00:00

Fuzzer

[libFuzzer] allow users to supply their own implementation of rand

2015-07-24 01:06:40 +00:00

IR

IR: Expose the method 'getLocalSlot' in the module slot tracker.

2015-07-27 22:31:04 +00:00

IRReader

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LibDriver

Add support for producing thin archives in llvm-lib.

2015-07-17 16:01:11 +00:00

LineEditor

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Linker

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LTO

Remove access to the DataLayout in the TargetMachine

2015-07-24 16:04:22 +00:00

MC

[llvm-mc] Add --no-warn flag with -W alias to disable outputting warnings while assembling.

2015-07-27 22:39:14 +00:00

Object

Fix fetching the symbol table of a thin archive.

2015-07-22 19:34:26 +00:00

Option

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Passes

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ProfileData

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Support

- Added support for parsing HWDiv features using Target Parser.

2015-07-27 22:26:59 +00:00

TableGen

[TableGen] Emit the correct error message.

2015-07-27 17:22:19 +00:00

Target

WebAssembly: add a generic CPU

2015-07-27 23:25:54 +00:00

Transforms

[LSR] Generate and use zero extends

2015-07-27 23:27:51 +00:00

CMakeLists.txt

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LLVMBuild.txt

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Makefile

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