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aac33cfc08
Enabling HasAVX512{DQ,BW,VL} predicates.
Adding VK2, VK4, VK32, VK64 masked register classes.
Adding new types (v64i8, v32i16) to VR512.
Extending calling conventions for new types (v64i8, v32i16)
Patch by Zinovy Nis <zinovy.y.nis@intel.com>
Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213545 91177308-0d34-0410-b5e6-96231b3b80d8
663 lines
26 KiB
TableGen
663 lines
26 KiB
TableGen
//===-- X86CallingConv.td - Calling Conventions X86 32/64 --*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This describes the calling conventions for the X86-32 and X86-64
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// architectures.
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//
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//===----------------------------------------------------------------------===//
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/// CCIfSubtarget - Match if the current subtarget has a feature F.
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class CCIfSubtarget<string F, CCAction A>
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: CCIf<!strconcat("State.getTarget().getSubtarget<X86Subtarget>().", F), A>;
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//===----------------------------------------------------------------------===//
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// Return Value Calling Conventions
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//===----------------------------------------------------------------------===//
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// Return-value conventions common to all X86 CC's.
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def RetCC_X86Common : CallingConv<[
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// Scalar values are returned in AX first, then DX. For i8, the ABI
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// requires the values to be in AL and AH, however this code uses AL and DL
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// instead. This is because using AH for the second register conflicts with
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// the way LLVM does multiple return values -- a return of {i16,i8} would end
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// up in AX and AH, which overlap. Front-ends wishing to conform to the ABI
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// for functions that return two i8 values are currently expected to pack the
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// values into an i16 (which uses AX, and thus AL:AH).
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//
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// For code that doesn't care about the ABI, we allow returning more than two
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// integer values in registers.
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CCIfType<[i8] , CCAssignToReg<[AL, DL, CL]>>,
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CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>,
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CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>,
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CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX]>>,
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// Vector types are returned in XMM0 and XMM1, when they fit. XMM2 and XMM3
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// can only be used by ABI non-compliant code. If the target doesn't have XMM
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// registers, it won't have vector types.
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CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
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CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
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// 256-bit vectors are returned in YMM0 and XMM1, when they fit. YMM2 and YMM3
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// can only be used by ABI non-compliant code. This vector type is only
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// supported while using the AVX target feature.
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CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
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CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>,
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// 512-bit vectors are returned in ZMM0 and ZMM1, when they fit. ZMM2 and ZMM3
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// can only be used by ABI non-compliant code. This vector type is only
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// supported while using the AVX-512 target feature.
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CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
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CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>,
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// MMX vector types are always returned in MM0. If the target doesn't have
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// MM0, it doesn't support these vector types.
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CCIfType<[x86mmx], CCAssignToReg<[MM0]>>,
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// Long double types are always returned in ST0 (even with SSE).
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CCIfType<[f80], CCAssignToReg<[ST0, ST1]>>
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]>;
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// X86-32 C return-value convention.
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def RetCC_X86_32_C : CallingConv<[
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// The X86-32 calling convention returns FP values in ST0, unless marked
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// with "inreg" (used here to distinguish one kind of reg from another,
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// weirdly; this is really the sse-regparm calling convention) in which
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// case they use XMM0, otherwise it is the same as the common X86 calling
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// conv.
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CCIfInReg<CCIfSubtarget<"hasSSE2()",
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CCIfType<[f32, f64], CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
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CCIfType<[f32,f64], CCAssignToReg<[ST0, ST1]>>,
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CCDelegateTo<RetCC_X86Common>
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]>;
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// X86-32 FastCC return-value convention.
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def RetCC_X86_32_Fast : CallingConv<[
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// The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has
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// SSE2.
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// This can happen when a float, 2 x float, or 3 x float vector is split by
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// target lowering, and is returned in 1-3 sse regs.
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CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
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CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
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// For integers, ECX can be used as an extra return register
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CCIfType<[i8], CCAssignToReg<[AL, DL, CL]>>,
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CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>,
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CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>,
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// Otherwise, it is the same as the common X86 calling convention.
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CCDelegateTo<RetCC_X86Common>
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]>;
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// Intel_OCL_BI return-value convention.
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def RetCC_Intel_OCL_BI : CallingConv<[
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// Vector types are returned in XMM0,XMM1,XMMM2 and XMM3.
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CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64],
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CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
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// 256-bit FP vectors
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// No more than 4 registers
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CCIfType<[v8f32, v4f64, v8i32, v4i64],
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CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>,
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// 512-bit FP vectors
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CCIfType<[v16f32, v8f64, v16i32, v8i64],
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CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>,
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// i32, i64 in the standard way
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CCDelegateTo<RetCC_X86Common>
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]>;
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// X86-32 HiPE return-value convention.
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def RetCC_X86_32_HiPE : CallingConv<[
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// Promote all types to i32
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CCIfType<[i8, i16], CCPromoteToType<i32>>,
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// Return: HP, P, VAL1, VAL2
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CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX]>>
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]>;
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// X86-64 C return-value convention.
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def RetCC_X86_64_C : CallingConv<[
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// The X86-64 calling convention always returns FP values in XMM0.
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CCIfType<[f32], CCAssignToReg<[XMM0, XMM1]>>,
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CCIfType<[f64], CCAssignToReg<[XMM0, XMM1]>>,
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// MMX vector types are always returned in XMM0.
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CCIfType<[x86mmx], CCAssignToReg<[XMM0, XMM1]>>,
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CCDelegateTo<RetCC_X86Common>
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]>;
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// X86-Win64 C return-value convention.
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def RetCC_X86_Win64_C : CallingConv<[
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// The X86-Win64 calling convention always returns __m64 values in RAX.
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CCIfType<[x86mmx], CCBitConvertToType<i64>>,
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// Otherwise, everything is the same as 'normal' X86-64 C CC.
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CCDelegateTo<RetCC_X86_64_C>
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]>;
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// X86-64 HiPE return-value convention.
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def RetCC_X86_64_HiPE : CallingConv<[
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// Promote all types to i64
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CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
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// Return: HP, P, VAL1, VAL2
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CCIfType<[i64], CCAssignToReg<[R15, RBP, RAX, RDX]>>
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]>;
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// X86-64 WebKit_JS return-value convention.
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def RetCC_X86_64_WebKit_JS : CallingConv<[
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// Promote all types to i64
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CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
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// Return: RAX
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CCIfType<[i64], CCAssignToReg<[RAX]>>
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]>;
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// X86-64 AnyReg return-value convention. No explicit register is specified for
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// the return-value. The register allocator is allowed and expected to choose
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// any free register.
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//
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// This calling convention is currently only supported by the stackmap and
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// patchpoint intrinsics. All other uses will result in an assert on Debug
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// builds. On Release builds we fallback to the X86 C calling convention.
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def RetCC_X86_64_AnyReg : CallingConv<[
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CCCustom<"CC_X86_AnyReg_Error">
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]>;
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// This is the root return-value convention for the X86-32 backend.
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def RetCC_X86_32 : CallingConv<[
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// If FastCC, use RetCC_X86_32_Fast.
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CCIfCC<"CallingConv::Fast", CCDelegateTo<RetCC_X86_32_Fast>>,
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// If HiPE, use RetCC_X86_32_HiPE.
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CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_32_HiPE>>,
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// Otherwise, use RetCC_X86_32_C.
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CCDelegateTo<RetCC_X86_32_C>
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]>;
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// This is the root return-value convention for the X86-64 backend.
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def RetCC_X86_64 : CallingConv<[
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// HiPE uses RetCC_X86_64_HiPE
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CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_64_HiPE>>,
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// Handle JavaScript calls.
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CCIfCC<"CallingConv::WebKit_JS", CCDelegateTo<RetCC_X86_64_WebKit_JS>>,
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CCIfCC<"CallingConv::AnyReg", CCDelegateTo<RetCC_X86_64_AnyReg>>,
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// Handle explicit CC selection
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CCIfCC<"CallingConv::X86_64_Win64", CCDelegateTo<RetCC_X86_Win64_C>>,
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CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<RetCC_X86_64_C>>,
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// Mingw64 and native Win64 use Win64 CC
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CCIfSubtarget<"isTargetWin64()", CCDelegateTo<RetCC_X86_Win64_C>>,
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// Otherwise, drop to normal X86-64 CC
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CCDelegateTo<RetCC_X86_64_C>
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]>;
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// This is the return-value convention used for the entire X86 backend.
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def RetCC_X86 : CallingConv<[
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// Check if this is the Intel OpenCL built-ins calling convention
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CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<RetCC_Intel_OCL_BI>>,
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CCIfSubtarget<"is64Bit()", CCDelegateTo<RetCC_X86_64>>,
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CCDelegateTo<RetCC_X86_32>
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]>;
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//===----------------------------------------------------------------------===//
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// X86-64 Argument Calling Conventions
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//===----------------------------------------------------------------------===//
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def CC_X86_64_C : CallingConv<[
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// Handles byval parameters.
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CCIfByVal<CCPassByVal<8, 8>>,
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// Promote i8/i16 arguments to i32.
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CCIfType<[i8, i16], CCPromoteToType<i32>>,
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// The 'nest' parameter, if any, is passed in R10.
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CCIfNest<CCAssignToReg<[R10]>>,
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// The first 6 integer arguments are passed in integer registers.
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CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D, R9D]>>,
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CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
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// The first 8 MMX vector arguments are passed in XMM registers on Darwin.
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CCIfType<[x86mmx],
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CCIfSubtarget<"isTargetDarwin()",
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CCIfSubtarget<"hasSSE2()",
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CCPromoteToType<v2i64>>>>,
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// The first 8 FP/Vector arguments are passed in XMM registers.
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CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
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CCIfSubtarget<"hasSSE1()",
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CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>,
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// The first 8 256-bit vector arguments are passed in YMM registers, unless
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// this is a vararg function.
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// FIXME: This isn't precisely correct; the x86-64 ABI document says that
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// fixed arguments to vararg functions are supposed to be passed in
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// registers. Actually modeling that would be a lot of work, though.
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CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
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CCIfSubtarget<"hasFp256()",
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CCAssignToReg<[YMM0, YMM1, YMM2, YMM3,
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YMM4, YMM5, YMM6, YMM7]>>>>,
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// The first 8 512-bit vector arguments are passed in ZMM registers.
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CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
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CCIfSubtarget<"hasAVX512()",
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CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7]>>>>,
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// Integer/FP values get stored in stack slots that are 8 bytes in size and
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// 8-byte aligned if there are no more registers to hold them.
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CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
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// Long doubles get stack slots whose size and alignment depends on the
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// subtarget.
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CCIfType<[f80], CCAssignToStack<0, 0>>,
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// Vectors get 16-byte stack slots that are 16-byte aligned.
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CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
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// 256-bit vectors get 32-byte stack slots that are 32-byte aligned.
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CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
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CCAssignToStack<32, 32>>,
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// 512-bit vectors get 64-byte stack slots that are 64-byte aligned.
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CCIfType<[v16i32, v8i64, v16f32, v8f64],
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CCAssignToStack<64, 64>>
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]>;
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// Calling convention used on Win64
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def CC_X86_Win64_C : CallingConv<[
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// FIXME: Handle byval stuff.
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// FIXME: Handle varargs.
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// Promote i8/i16 arguments to i32.
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CCIfType<[i8, i16], CCPromoteToType<i32>>,
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// The 'nest' parameter, if any, is passed in R10.
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CCIfNest<CCAssignToReg<[R10]>>,
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// 128 bit vectors are passed by pointer
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CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCPassIndirect<i64>>,
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// 256 bit vectors are passed by pointer
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CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>,
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// 512 bit vectors are passed by pointer
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CCIfType<[v16i32, v16f32, v8f64, v8i64], CCPassIndirect<i64>>,
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// The first 4 MMX vector arguments are passed in GPRs.
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CCIfType<[x86mmx], CCBitConvertToType<i64>>,
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// The first 4 integer arguments are passed in integer registers.
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CCIfType<[i32], CCAssignToRegWithShadow<[ECX , EDX , R8D , R9D ],
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[XMM0, XMM1, XMM2, XMM3]>>,
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// Do not pass the sret argument in RCX, the Win64 thiscall calling
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// convention requires "this" to be passed in RCX.
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CCIfCC<"CallingConv::X86_ThisCall",
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CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[RDX , R8 , R9 ],
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[XMM1, XMM2, XMM3]>>>>,
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CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
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[XMM0, XMM1, XMM2, XMM3]>>,
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// The first 4 FP/Vector arguments are passed in XMM registers.
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CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
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CCAssignToRegWithShadow<[XMM0, XMM1, XMM2, XMM3],
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[RCX , RDX , R8 , R9 ]>>,
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// Integer/FP values get stored in stack slots that are 8 bytes in size and
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// 8-byte aligned if there are no more registers to hold them.
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CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
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// Long doubles get stack slots whose size and alignment depends on the
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// subtarget.
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CCIfType<[f80], CCAssignToStack<0, 0>>
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]>;
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def CC_X86_64_GHC : CallingConv<[
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// Promote i8/i16/i32 arguments to i64.
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CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
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// Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim
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CCIfType<[i64],
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CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
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// Pass in STG registers: F1, F2, F3, F4, D1, D2
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CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
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CCIfSubtarget<"hasSSE1()",
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CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>
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]>;
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def CC_X86_64_HiPE : CallingConv<[
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// Promote i8/i16/i32 arguments to i64.
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CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
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// Pass in VM's registers: HP, P, ARG0, ARG1, ARG2, ARG3
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CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>,
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// Integer/FP values get stored in stack slots that are 8 bytes in size and
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// 8-byte aligned if there are no more registers to hold them.
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CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>
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]>;
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def CC_X86_64_WebKit_JS : CallingConv<[
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// Promote i8/i16 arguments to i32.
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CCIfType<[i8, i16], CCPromoteToType<i32>>,
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// Only the first integer argument is passed in register.
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CCIfType<[i32], CCAssignToReg<[EAX]>>,
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CCIfType<[i64], CCAssignToReg<[RAX]>>,
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// The remaining integer arguments are passed on the stack. 32bit integer and
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// floating-point arguments are aligned to 4 byte and stored in 4 byte slots.
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// 64bit integer and floating-point arguments are aligned to 8 byte and stored
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// in 8 byte stack slots.
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CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
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CCIfType<[i64, f64], CCAssignToStack<8, 8>>
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]>;
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// No explicit register is specified for the AnyReg calling convention. The
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// register allocator may assign the arguments to any free register.
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//
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// This calling convention is currently only supported by the stackmap and
|
|
// patchpoint intrinsics. All other uses will result in an assert on Debug
|
|
// builds. On Release builds we fallback to the X86 C calling convention.
|
|
def CC_X86_64_AnyReg : CallingConv<[
|
|
CCCustom<"CC_X86_AnyReg_Error">
|
|
]>;
|
|
|
|
//===----------------------------------------------------------------------===//
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// X86 C Calling Convention
|
|
//===----------------------------------------------------------------------===//
|
|
|
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/// CC_X86_32_Common - In all X86-32 calling conventions, extra integers and FP
|
|
/// values are spilled on the stack, and the first 4 vector values go in XMM
|
|
/// regs.
|
|
def CC_X86_32_Common : CallingConv<[
|
|
// Handles byval parameters.
|
|
CCIfByVal<CCPassByVal<4, 4>>,
|
|
|
|
// The first 3 float or double arguments, if marked 'inreg' and if the call
|
|
// is not a vararg call and if SSE2 is available, are passed in SSE registers.
|
|
CCIfNotVarArg<CCIfInReg<CCIfType<[f32,f64],
|
|
CCIfSubtarget<"hasSSE2()",
|
|
CCAssignToReg<[XMM0,XMM1,XMM2]>>>>>,
|
|
|
|
// The first 3 __m64 vector arguments are passed in mmx registers if the
|
|
// call is not a vararg call.
|
|
CCIfNotVarArg<CCIfType<[x86mmx],
|
|
CCAssignToReg<[MM0, MM1, MM2]>>>,
|
|
|
|
// Integer/Float values get stored in stack slots that are 4 bytes in
|
|
// size and 4-byte aligned.
|
|
CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
|
|
|
|
// Doubles get 8-byte slots that are 4-byte aligned.
|
|
CCIfType<[f64], CCAssignToStack<8, 4>>,
|
|
|
|
// Long doubles get slots whose size depends on the subtarget.
|
|
CCIfType<[f80], CCAssignToStack<0, 4>>,
|
|
|
|
// The first 4 SSE vector arguments are passed in XMM registers.
|
|
CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
|
|
CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>>,
|
|
|
|
// The first 4 AVX 256-bit vector arguments are passed in YMM registers.
|
|
CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
|
|
CCIfSubtarget<"hasFp256()",
|
|
CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>>>,
|
|
|
|
// Other SSE vectors get 16-byte stack slots that are 16-byte aligned.
|
|
CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
|
|
|
|
// 256-bit AVX vectors get 32-byte stack slots that are 32-byte aligned.
|
|
CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
|
|
CCAssignToStack<32, 32>>,
|
|
|
|
// __m64 vectors get 8-byte stack slots that are 4-byte aligned. They are
|
|
// passed in the parameter area.
|
|
CCIfType<[x86mmx], CCAssignToStack<8, 4>>]>;
|
|
|
|
def CC_X86_32_C : CallingConv<[
|
|
// Promote i8/i16 arguments to i32.
|
|
CCIfType<[i8, i16], CCPromoteToType<i32>>,
|
|
|
|
// The 'nest' parameter, if any, is passed in ECX.
|
|
CCIfNest<CCAssignToReg<[ECX]>>,
|
|
|
|
// The first 3 integer arguments, if marked 'inreg' and if the call is not
|
|
// a vararg call, are passed in integer registers.
|
|
CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>>>,
|
|
|
|
// Otherwise, same as everything else.
|
|
CCDelegateTo<CC_X86_32_Common>
|
|
]>;
|
|
|
|
def CC_X86_32_FastCall : CallingConv<[
|
|
// Promote i8/i16 arguments to i32.
|
|
CCIfType<[i8, i16], CCPromoteToType<i32>>,
|
|
|
|
// The 'nest' parameter, if any, is passed in EAX.
|
|
CCIfNest<CCAssignToReg<[EAX]>>,
|
|
|
|
// The first 2 integer arguments are passed in ECX/EDX
|
|
CCIfInReg<CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>>,
|
|
|
|
// Otherwise, same as everything else.
|
|
CCDelegateTo<CC_X86_32_Common>
|
|
]>;
|
|
|
|
def CC_X86_32_ThisCall_Common : CallingConv<[
|
|
// The first integer argument is passed in ECX
|
|
CCIfType<[i32], CCAssignToReg<[ECX]>>,
|
|
|
|
// Otherwise, same as everything else.
|
|
CCDelegateTo<CC_X86_32_Common>
|
|
]>;
|
|
|
|
def CC_X86_32_ThisCall_Mingw : CallingConv<[
|
|
// Promote i8/i16 arguments to i32.
|
|
CCIfType<[i8, i16], CCPromoteToType<i32>>,
|
|
|
|
CCDelegateTo<CC_X86_32_ThisCall_Common>
|
|
]>;
|
|
|
|
def CC_X86_32_ThisCall_Win : CallingConv<[
|
|
// Promote i8/i16 arguments to i32.
|
|
CCIfType<[i8, i16], CCPromoteToType<i32>>,
|
|
|
|
// Pass sret arguments indirectly through stack.
|
|
CCIfSRet<CCAssignToStack<4, 4>>,
|
|
|
|
CCDelegateTo<CC_X86_32_ThisCall_Common>
|
|
]>;
|
|
|
|
def CC_X86_32_ThisCall : CallingConv<[
|
|
CCIfSubtarget<"isTargetCygMing()", CCDelegateTo<CC_X86_32_ThisCall_Mingw>>,
|
|
CCDelegateTo<CC_X86_32_ThisCall_Win>
|
|
]>;
|
|
|
|
def CC_X86_32_FastCC : CallingConv<[
|
|
// Handles byval parameters. Note that we can't rely on the delegation
|
|
// to CC_X86_32_Common for this because that happens after code that
|
|
// puts arguments in registers.
|
|
CCIfByVal<CCPassByVal<4, 4>>,
|
|
|
|
// Promote i8/i16 arguments to i32.
|
|
CCIfType<[i8, i16], CCPromoteToType<i32>>,
|
|
|
|
// The 'nest' parameter, if any, is passed in EAX.
|
|
CCIfNest<CCAssignToReg<[EAX]>>,
|
|
|
|
// The first 2 integer arguments are passed in ECX/EDX
|
|
CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,
|
|
|
|
// The first 3 float or double arguments, if the call is not a vararg
|
|
// call and if SSE2 is available, are passed in SSE registers.
|
|
CCIfNotVarArg<CCIfType<[f32,f64],
|
|
CCIfSubtarget<"hasSSE2()",
|
|
CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
|
|
|
|
// Doubles get 8-byte slots that are 8-byte aligned.
|
|
CCIfType<[f64], CCAssignToStack<8, 8>>,
|
|
|
|
// Otherwise, same as everything else.
|
|
CCDelegateTo<CC_X86_32_Common>
|
|
]>;
|
|
|
|
def CC_X86_32_GHC : CallingConv<[
|
|
// Promote i8/i16 arguments to i32.
|
|
CCIfType<[i8, i16], CCPromoteToType<i32>>,
|
|
|
|
// Pass in STG registers: Base, Sp, Hp, R1
|
|
CCIfType<[i32], CCAssignToReg<[EBX, EBP, EDI, ESI]>>
|
|
]>;
|
|
|
|
def CC_X86_32_HiPE : CallingConv<[
|
|
// Promote i8/i16 arguments to i32.
|
|
CCIfType<[i8, i16], CCPromoteToType<i32>>,
|
|
|
|
// Pass in VM's registers: HP, P, ARG0, ARG1, ARG2
|
|
CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX, ECX]>>,
|
|
|
|
// Integer/Float values get stored in stack slots that are 4 bytes in
|
|
// size and 4-byte aligned.
|
|
CCIfType<[i32, f32], CCAssignToStack<4, 4>>
|
|
]>;
|
|
|
|
// X86-64 Intel OpenCL built-ins calling convention.
|
|
def CC_Intel_OCL_BI : CallingConv<[
|
|
|
|
CCIfType<[i32], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[ECX, EDX, R8D, R9D]>>>,
|
|
CCIfType<[i64], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[RCX, RDX, R8, R9 ]>>>,
|
|
|
|
CCIfType<[i32], CCIfSubtarget<"is64Bit()", CCAssignToReg<[EDI, ESI, EDX, ECX]>>>,
|
|
CCIfType<[i64], CCIfSubtarget<"is64Bit()", CCAssignToReg<[RDI, RSI, RDX, RCX]>>>,
|
|
|
|
CCIfType<[i32], CCAssignToStack<4, 4>>,
|
|
|
|
// The SSE vector arguments are passed in XMM registers.
|
|
CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64],
|
|
CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>,
|
|
|
|
// The 256-bit vector arguments are passed in YMM registers.
|
|
CCIfType<[v8f32, v4f64, v8i32, v4i64],
|
|
CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>,
|
|
|
|
// The 512-bit vector arguments are passed in ZMM registers.
|
|
CCIfType<[v16f32, v8f64, v16i32, v8i64],
|
|
CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3]>>,
|
|
|
|
CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>,
|
|
CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64_C>>,
|
|
CCDelegateTo<CC_X86_32_C>
|
|
]>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// X86 Root Argument Calling Conventions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// This is the root argument convention for the X86-32 backend.
|
|
def CC_X86_32 : CallingConv<[
|
|
CCIfCC<"CallingConv::X86_FastCall", CCDelegateTo<CC_X86_32_FastCall>>,
|
|
CCIfCC<"CallingConv::X86_ThisCall", CCDelegateTo<CC_X86_32_ThisCall>>,
|
|
CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_X86_32_FastCC>>,
|
|
CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_32_GHC>>,
|
|
CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_32_HiPE>>,
|
|
|
|
// Otherwise, drop to normal X86-32 CC
|
|
CCDelegateTo<CC_X86_32_C>
|
|
]>;
|
|
|
|
// This is the root argument convention for the X86-64 backend.
|
|
def CC_X86_64 : CallingConv<[
|
|
CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_64_GHC>>,
|
|
CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_64_HiPE>>,
|
|
CCIfCC<"CallingConv::WebKit_JS", CCDelegateTo<CC_X86_64_WebKit_JS>>,
|
|
CCIfCC<"CallingConv::AnyReg", CCDelegateTo<CC_X86_64_AnyReg>>,
|
|
CCIfCC<"CallingConv::X86_64_Win64", CCDelegateTo<CC_X86_Win64_C>>,
|
|
CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<CC_X86_64_C>>,
|
|
|
|
// Mingw64 and native Win64 use Win64 CC
|
|
CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>,
|
|
|
|
// Otherwise, drop to normal X86-64 CC
|
|
CCDelegateTo<CC_X86_64_C>
|
|
]>;
|
|
|
|
// This is the argument convention used for the entire X86 backend.
|
|
def CC_X86 : CallingConv<[
|
|
CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<CC_Intel_OCL_BI>>,
|
|
CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64>>,
|
|
CCDelegateTo<CC_X86_32>
|
|
]>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Callee-saved Registers.
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def CSR_NoRegs : CalleeSavedRegs<(add)>;
|
|
|
|
def CSR_32 : CalleeSavedRegs<(add ESI, EDI, EBX, EBP)>;
|
|
def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>;
|
|
|
|
def CSR_32EHRet : CalleeSavedRegs<(add EAX, EDX, CSR_32)>;
|
|
def CSR_64EHRet : CalleeSavedRegs<(add RAX, RDX, CSR_64)>;
|
|
|
|
def CSR_Win64 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15,
|
|
(sequence "XMM%u", 6, 15))>;
|
|
|
|
// All GPRs - except r11
|
|
def CSR_64_RT_MostRegs : CalleeSavedRegs<(add CSR_64, RAX, RCX, RDX, RSI, RDI,
|
|
R8, R9, R10, RSP)>;
|
|
|
|
// All registers - except r11
|
|
def CSR_64_RT_AllRegs : CalleeSavedRegs<(add CSR_64_RT_MostRegs,
|
|
(sequence "XMM%u", 0, 15))>;
|
|
def CSR_64_RT_AllRegs_AVX : CalleeSavedRegs<(add CSR_64_RT_MostRegs,
|
|
(sequence "YMM%u", 0, 15))>;
|
|
|
|
def CSR_64_MostRegs : CalleeSavedRegs<(add RBX, RCX, RDX, RSI, RDI, R8, R9, R10,
|
|
R11, R12, R13, R14, R15, RBP,
|
|
(sequence "XMM%u", 0, 15))>;
|
|
|
|
def CSR_64_AllRegs : CalleeSavedRegs<(add CSR_64_MostRegs, RAX, RSP,
|
|
(sequence "XMM%u", 16, 31))>;
|
|
def CSR_64_AllRegs_AVX : CalleeSavedRegs<(sub (add CSR_64_MostRegs, RAX, RSP,
|
|
(sequence "YMM%u", 0, 31)),
|
|
(sequence "XMM%u", 0, 15))>;
|
|
|
|
// Standard C + YMM6-15
|
|
def CSR_Win64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12,
|
|
R13, R14, R15,
|
|
(sequence "YMM%u", 6, 15))>;
|
|
|
|
def CSR_Win64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI,
|
|
R12, R13, R14, R15,
|
|
(sequence "ZMM%u", 6, 21),
|
|
K4, K5, K6, K7)>;
|
|
//Standard C + XMM 8-15
|
|
def CSR_64_Intel_OCL_BI : CalleeSavedRegs<(add CSR_64,
|
|
(sequence "XMM%u", 8, 15))>;
|
|
|
|
//Standard C + YMM 8-15
|
|
def CSR_64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add CSR_64,
|
|
(sequence "YMM%u", 8, 15))>;
|
|
|
|
def CSR_64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RDI, RSI, R14, R15,
|
|
(sequence "ZMM%u", 16, 31),
|
|
K4, K5, K6, K7)>;
|