mirror of
https://github.com/RPCS3/llvm.git
synced 2024-11-28 14:10:55 +00:00
49683f3c96
The new target machines are: nvptx (old ptx32) => 32-bit PTX nvptx64 (old ptx64) => 64-bit PTX The sources are based on the internal NVIDIA NVPTX back-end, and contain more functionality than the current PTX back-end currently provides. NV_CONTRIB git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156196 91177308-0d34-0410-b5e6-96231b3b80d8
73 lines
1.7 KiB
LLVM
73 lines
1.7 KiB
LLVM
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
|
|
; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s
|
|
|
|
;; These tests should run for all targets
|
|
|
|
;;===-- Basic instruction selection tests ---------------------------------===;;
|
|
|
|
|
|
;;; f64
|
|
|
|
define double @fadd_f64(double %a, double %b) {
|
|
; CHECK: add.f64 %fl{{[0-9]+}}, %fl{{[0-9]+}}, %fl{{[0-9]+}}
|
|
; CHECK: ret
|
|
%ret = fadd double %a, %b
|
|
ret double %ret
|
|
}
|
|
|
|
define double @fsub_f64(double %a, double %b) {
|
|
; CHECK: sub.f64 %fl{{[0-9]+}}, %fl{{[0-9]+}}, %fl{{[0-9]+}}
|
|
; CHECK: ret
|
|
%ret = fsub double %a, %b
|
|
ret double %ret
|
|
}
|
|
|
|
define double @fmul_f64(double %a, double %b) {
|
|
; CHECK: mul.f64 %fl{{[0-9]+}}, %fl{{[0-9]+}}, %fl{{[0-9]+}}
|
|
; CHECK: ret
|
|
%ret = fmul double %a, %b
|
|
ret double %ret
|
|
}
|
|
|
|
define double @fdiv_f64(double %a, double %b) {
|
|
; CHECK: div.rn.f64 %fl{{[0-9]+}}, %fl{{[0-9]+}}, %fl{{[0-9]+}}
|
|
; CHECK: ret
|
|
%ret = fdiv double %a, %b
|
|
ret double %ret
|
|
}
|
|
|
|
;; PTX does not have a floating-point rem instruction
|
|
|
|
|
|
;;; f32
|
|
|
|
define float @fadd_f32(float %a, float %b) {
|
|
; CHECK: add.f32 %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}
|
|
; CHECK: ret
|
|
%ret = fadd float %a, %b
|
|
ret float %ret
|
|
}
|
|
|
|
define float @fsub_f32(float %a, float %b) {
|
|
; CHECK: sub.f32 %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}
|
|
; CHECK: ret
|
|
%ret = fsub float %a, %b
|
|
ret float %ret
|
|
}
|
|
|
|
define float @fmul_f32(float %a, float %b) {
|
|
; CHECK: mul.f32 %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}
|
|
; CHECK: ret
|
|
%ret = fmul float %a, %b
|
|
ret float %ret
|
|
}
|
|
|
|
define float @fdiv_f32(float %a, float %b) {
|
|
; CHECK: div.rn.f32 %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}
|
|
; CHECK: ret
|
|
%ret = fdiv float %a, %b
|
|
ret float %ret
|
|
}
|
|
|
|
;; PTX does not have a floating-point rem instruction
|