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https://github.com/RPCS3/llvm.git
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Daniel Sanders
d31f3f6227
There's a strange assertion on two of the Green Dragon bots that goes away when this is reverted. The assertion is in RegBankAlloc and if it is this commit then -verify-machine-instrs should have caught it earlier in the pipeline. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343546 91177308-0d34-0410-b5e6-96231b3b80d8
42 lines
1.3 KiB
C++
42 lines
1.3 KiB
C++
//== ---lib/CodeGen/GlobalISel/GICombinerHelper.cpp --------------------- == //
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/GlobalISel/Utils.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#define DEBUG_TYPE "gi-combine"
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using namespace llvm;
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CombinerHelper::CombinerHelper(MachineIRBuilder &B) :
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Builder(B), MRI(Builder.getMF().getRegInfo()) {}
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bool CombinerHelper::tryCombineCopy(MachineInstr &MI) {
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if (MI.getOpcode() != TargetOpcode::COPY)
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return false;
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unsigned DstReg = MI.getOperand(0).getReg();
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unsigned SrcReg = MI.getOperand(1).getReg();
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LLT DstTy = MRI.getType(DstReg);
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LLT SrcTy = MRI.getType(SrcReg);
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// Simple Copy Propagation.
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// a(sx) = COPY b(sx) -> Replace all uses of a with b.
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if (DstTy.isValid() && SrcTy.isValid() && DstTy == SrcTy) {
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MI.eraseFromParent();
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MRI.replaceRegWith(DstReg, SrcReg);
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return true;
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}
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return false;
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}
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bool CombinerHelper::tryCombine(MachineInstr &MI) {
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return tryCombineCopy(MI);
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}
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