Ana Pazos ab2b9db490 [RISCV] Fix decoding of invalid instruction with C extension enabled. ...

Summary:
The illegal instruction 0x00 0x00 is being wrongly decoded as
c.addi4spn with 0 immediate.

The invalid instruction 0x01 0x61 is being wrongly decoded as
c.addi16sp with 0 immediate.

This bug was uncovered by a LLVM MC Disassembler Protocol Buffer Fuzzer
for the RISC-V assembly language.

Reviewers: asb

Reviewed By: asb

Subscribers: rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, asb

Differential Revision: https://reviews.llvm.org/D51815

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342159 91177308-0d34-0410-b5e6-96231b3b80d8

2018-09-13 18:21:19 +00:00

..

CMakeLists.txt

[RISCV] Add support for disassembly

2017-09-17 14:36:28 +00:00

LLVMBuild.txt

[RISCV] Add support for disassembly

2017-09-17 14:36:28 +00:00

RISCVDisassembler.cpp

[RISCV] Fix decoding of invalid instruction with C extension enabled.

2018-09-13 18:21:19 +00:00