llvm/MC at 4eeee88e912cc03208b5ead91563a7519ec4ab73 - llvm

RPCS3/llvm

mirror of https://github.com/RPCS3/llvm.git synced 2025-02-11 05:17:36 +00:00

History

Saleem Abdulrasool 4eeee88e91 ARM IAS: support implicit immediate 0s for {LD,ST}R{B,}T

The ARM ARM indicates the mnemonics as follows:

  ldrbt{<c>}{<q>} <Rt>, [<Rn>], {, #+/-<imm>}
  ldrt{<c>}{<q>} <Rt>, [<Rn>] {, #+/-<imm>}
  strbt{<c>}{<q>} <Rt>, [<Rn>] {, #<imm>}
  strt{<c>}{<q>} <Rt>, [<Rn>] {, #+/-<imm>}

This improves the parser to deal with the implicit immediate 0 for the mnemonics
as per the specification.

Thanks to Joerg Sonnenberger for the tests!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198914 91177308-0d34-0410-b5e6-96231b3b80d8

2014-01-10 04:38:31 +00:00

AArch64

[AArch64][NEON] Added UXTL and UXTL2 instruction aliases

2014-01-08 21:02:13 +00:00

ARM

ARM IAS: support implicit immediate 0s for {LD,ST}R{B,}T

2014-01-10 04:38:31 +00:00

AsmParser

Mark the 64-bit x86 push/pop instructions as In64BitMode. Mark the corresponding 32-bit versions with the same encodings Not64BitMode. Remove hack from tablegen disassembler table emitter. Fix bad test.

2014-01-05 01:35:51 +00:00

COFF

Add the .secidx test I've forgotten to svn add in 197826