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https://github.com/RPCS3/llvm.git
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49901e7a48
The code for generating scalar base pointers in vectorizeMemoryInstruction is not needed. We currently scalarize all GEPs and maintain the scalarized values in VectorLoopValueMap. The GEP cloning in this unneeded code is the same as that in scalarizeInstruction. The test cases that changed as a result of this patch changed because we were able to reuse the scalarized GEP that we previously generated instead of cloning a new one. Differential Revision: https://reviews.llvm.org/D30587 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298615 91177308-0d34-0410-b5e6-96231b3b80d8
187 lines
6.7 KiB
LLVM
187 lines
6.7 KiB
LLVM
; RUN: opt -S -vectorize-num-stores-pred=1 -force-vector-width=1 -force-vector-interleave=2 -loop-vectorize -verify-loop-info -simplifycfg < %s | FileCheck %s --check-prefix=UNROLL
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; RUN: opt -S -vectorize-num-stores-pred=1 -force-vector-width=1 -force-vector-interleave=2 -loop-vectorize -verify-loop-info < %s | FileCheck %s --check-prefix=UNROLL-NOSIMPLIFY
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; RUN: opt -S -vectorize-num-stores-pred=1 -force-vector-width=2 -force-vector-interleave=1 -loop-vectorize -verify-loop-info -simplifycfg < %s | FileCheck %s --check-prefix=VEC
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target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
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; Test predication of stores.
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define i32 @test(i32* nocapture %f) #0 {
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entry:
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br label %for.body
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; VEC-LABEL: test
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; VEC: %[[v0:.+]] = add i64 %index, 0
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; VEC: %[[v2:.+]] = getelementptr inbounds i32, i32* %f, i64 %[[v0]]
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; VEC: %[[v8:.+]] = icmp sgt <2 x i32> %{{.*}}, <i32 100, i32 100>
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; VEC: %[[v10:.+]] = and <2 x i1> %[[v8]], <i1 true, i1 true>
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; VEC: %[[o1:.+]] = or <2 x i1> zeroinitializer, %[[v10]]
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; VEC: %[[v11:.+]] = extractelement <2 x i1> %[[o1]], i32 0
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; VEC: %[[v12:.+]] = icmp eq i1 %[[v11]], true
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; VEC: br i1 %[[v12]], label %[[cond:.+]], label %[[else:.+]]
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;
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; VEC: [[cond]]:
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; VEC: %[[v13:.+]] = extractelement <2 x i32> %wide.load, i32 0
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; VEC: %[[v9a:.+]] = add nsw i32 %[[v13]], 20
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; VEC: store i32 %[[v9a]], i32* %[[v2]], align 4
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; VEC: br label %[[else:.+]]
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;
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; VEC: [[else]]:
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; VEC: %[[v15:.+]] = extractelement <2 x i1> %[[o1]], i32 1
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; VEC: %[[v16:.+]] = icmp eq i1 %[[v15]], true
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; VEC: br i1 %[[v16]], label %[[cond2:.+]], label %[[else2:.+]]
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;
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; VEC: [[cond2]]:
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; VEC: %[[v17:.+]] = extractelement <2 x i32> %wide.load, i32 1
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; VEC: %[[v9b:.+]] = add nsw i32 %[[v17]], 20
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; VEC: %[[v1:.+]] = add i64 %index, 1
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; VEC: %[[v4:.+]] = getelementptr inbounds i32, i32* %f, i64 %[[v1]]
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; VEC: store i32 %[[v9b]], i32* %[[v4]], align 4
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; VEC: br label %[[else2:.+]]
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;
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; VEC: [[else2]]:
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; UNROLL-LABEL: test
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; UNROLL: vector.body:
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; UNROLL: %[[IND:[a-zA-Z0-9]+]] = add i64 %{{.*}}, 0
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; UNROLL: %[[IND1:[a-zA-Z0-9]+]] = add i64 %{{.*}}, 1
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; UNROLL: %[[v0:[a-zA-Z0-9]+]] = getelementptr inbounds i32, i32* %f, i64 %[[IND]]
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; UNROLL: %[[v1:[a-zA-Z0-9]+]] = getelementptr inbounds i32, i32* %f, i64 %[[IND1]]
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; UNROLL: %[[v2:[a-zA-Z0-9]+]] = load i32, i32* %[[v0]], align 4
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; UNROLL: %[[v3:[a-zA-Z0-9]+]] = load i32, i32* %[[v1]], align 4
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; UNROLL: %[[v4:[a-zA-Z0-9]+]] = icmp sgt i32 %[[v2]], 100
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; UNROLL: %[[v5:[a-zA-Z0-9]+]] = icmp sgt i32 %[[v3]], 100
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; UNROLL: %[[o1:[a-zA-Z0-9]+]] = or i1 false, %[[v4]]
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; UNROLL: %[[o2:[a-zA-Z0-9]+]] = or i1 false, %[[v5]]
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; UNROLL: %[[v8:[a-zA-Z0-9]+]] = icmp eq i1 %[[o1]], true
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; UNROLL: br i1 %[[v8]], label %[[cond:[a-zA-Z0-9.]+]], label %[[else:[a-zA-Z0-9.]+]]
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;
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; UNROLL: [[cond]]:
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; UNROLL: %[[v6:[a-zA-Z0-9]+]] = add nsw i32 %[[v2]], 20
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; UNROLL: store i32 %[[v6]], i32* %[[v0]], align 4
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; UNROLL: br label %[[else]]
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;
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; UNROLL: [[else]]:
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; UNROLL: %[[v9:[a-zA-Z0-9]+]] = icmp eq i1 %[[o2]], true
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; UNROLL: br i1 %[[v9]], label %[[cond2:[a-zA-Z0-9.]+]], label %[[else2:[a-zA-Z0-9.]+]]
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;
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; UNROLL: [[cond2]]:
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; UNROLL: %[[v7:[a-zA-Z0-9]+]] = add nsw i32 %[[v3]], 20
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; UNROLL: store i32 %[[v7]], i32* %[[v1]], align 4
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; UNROLL: br label %[[else2]]
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;
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; UNROLL: [[else2]]:
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for.body:
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%indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.inc ]
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%arrayidx = getelementptr inbounds i32, i32* %f, i64 %indvars.iv
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%0 = load i32, i32* %arrayidx, align 4
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%cmp1 = icmp sgt i32 %0, 100
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br i1 %cmp1, label %if.then, label %for.inc
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if.then:
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%add = add nsw i32 %0, 20
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store i32 %add, i32* %arrayidx, align 4
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br label %for.inc
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for.inc:
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond = icmp eq i64 %indvars.iv.next, 128
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br i1 %exitcond, label %for.end, label %for.body
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for.end:
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ret i32 0
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}
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; Track basic blocks when unrolling conditional blocks. This code used to assert
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; because we did not update the phi nodes with the proper predecessor in the
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; vectorized loop body.
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; PR18724
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; UNROLL-NOSIMPLIFY-LABEL: bug18724
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; UNROLL-NOSIMPLIFY: store i32
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; UNROLL-NOSIMPLIFY: store i32
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define void @bug18724() {
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entry:
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br label %for.body9
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for.body9:
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br i1 undef, label %for.inc26, label %for.body14
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for.body14:
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%indvars.iv3 = phi i64 [ %indvars.iv.next4, %for.inc23 ], [ undef, %for.body9 ]
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%iNewChunks.120 = phi i32 [ %iNewChunks.2, %for.inc23 ], [ undef, %for.body9 ]
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%arrayidx16 = getelementptr inbounds [768 x i32], [768 x i32]* undef, i64 0, i64 %indvars.iv3
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%tmp = load i32, i32* %arrayidx16, align 4
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br i1 undef, label %if.then18, label %for.inc23
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if.then18:
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store i32 2, i32* %arrayidx16, align 4
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%inc21 = add nsw i32 %iNewChunks.120, 1
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br label %for.inc23
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for.inc23:
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%iNewChunks.2 = phi i32 [ %inc21, %if.then18 ], [ %iNewChunks.120, %for.body14 ]
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%indvars.iv.next4 = add nsw i64 %indvars.iv3, 1
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%tmp1 = trunc i64 %indvars.iv3 to i32
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%cmp13 = icmp slt i32 %tmp1, 0
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br i1 %cmp13, label %for.body14, label %for.inc26
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for.inc26:
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%iNewChunks.1.lcssa = phi i32 [ undef, %for.body9 ], [ %iNewChunks.2, %for.inc23 ]
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unreachable
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}
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; VEC-LABEL: @minimal_bit_widths(
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;
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; In the test below, it's more profitable for the expression feeding the
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; conditional store to remain scalar. Since we can only type-shrink vector
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; types, we shouldn't try to represent the expression in a smaller type.
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;
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; VEC: vector.body:
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; VEC: %wide.load = load <2 x i8>, <2 x i8>* {{.*}}, align 1
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; VEC: br i1 {{.*}}, label %[[IF0:.+]], label %[[CONT0:.+]]
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; VEC: [[IF0]]:
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; VEC: %[[E0:.+]] = extractelement <2 x i8> %wide.load, i32 0
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; VEC: %[[Z0:.+]] = zext i8 %[[E0]] to i32
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; VEC: %[[T0:.+]] = trunc i32 %[[Z0]] to i8
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; VEC: store i8 %[[T0]], i8* {{.*}}, align 1
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; VEC: br label %[[CONT0]]
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; VEC: [[CONT0]]:
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; VEC: br i1 {{.*}}, label %[[IF1:.+]], label %[[CONT1:.+]]
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; VEC: [[IF1]]:
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; VEC: %[[E1:.+]] = extractelement <2 x i8> %wide.load, i32 1
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; VEC: %[[Z1:.+]] = zext i8 %[[E1]] to i32
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; VEC: %[[T1:.+]] = trunc i32 %[[Z1]] to i8
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; VEC: store i8 %[[T1]], i8* {{.*}}, align 1
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; VEC: br label %[[CONT1]]
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; VEC: [[CONT1]]:
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; VEC: br i1 {{.*}}, label %middle.block, label %vector.body
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;
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define void @minimal_bit_widths(i1 %c) {
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entry:
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br label %for.body
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for.body:
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%tmp0 = phi i64 [ %tmp6, %for.inc ], [ 0, %entry ]
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%tmp1 = phi i64 [ %tmp7, %for.inc ], [ undef, %entry ]
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%tmp2 = getelementptr i8, i8* undef, i64 %tmp0
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%tmp3 = load i8, i8* %tmp2, align 1
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br i1 %c, label %if.then, label %for.inc
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if.then:
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%tmp4 = zext i8 %tmp3 to i32
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%tmp5 = trunc i32 %tmp4 to i8
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store i8 %tmp5, i8* %tmp2, align 1
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br label %for.inc
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for.inc:
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%tmp6 = add nuw nsw i64 %tmp0, 1
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%tmp7 = add i64 %tmp1, -1
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%tmp8 = icmp eq i64 %tmp7, 0
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br i1 %tmp8, label %for.end, label %for.body
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for.end:
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ret void
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}
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