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72d5de4e70
For now, only add instruction definitions for basic ALU operations. Our initial target is a working MC layer rather than codegen, so appropriate SelectionDAG patterns will come later. Differential Revision: https://reviews.llvm.org/D23561 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285769 91177308-0d34-0410-b5e6-96231b3b80d8
28 lines
782 B
TableGen
28 lines
782 B
TableGen
//===-- RISCV.td - Describe the RISCV Target Machine -------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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include "RISCVRegisterInfo.td"
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include "RISCVInstrInfo.td"
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def RISCVInstrInfo : InstrInfo;
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def Feature64Bit : SubtargetFeature<"64bit", "HasRV64", "true",
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"Implements RV64">;
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def : ProcessorModel<"generic-rv32", NoSchedModel, []>;
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def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>;
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def RISCV : Target {
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let InstructionSet = RISCVInstrInfo;
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}
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