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ff1254b6f8
A number of backends (AArch64, MIPS, ARM) have been using MCContext::reportError to report issues such as out-of-range fixup values in their TgtAsmBackend. This is great, but because MCContext couldn't easily be threaded through to the adjustFixupValue helper function from its usual callsite (applyFixup), these backends ended up adding an MCContext* argument and adding another call to applyFixup to processFixupValue. Adding an MCContext parameter to applyFixup makes this unnecessary, and even better - applyFixup can take a reference to MCContext rather than a potentially null pointer. Differential Revision: https://reviews.llvm.org/D30264 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299529 91177308-0d34-0410-b5e6-96231b3b80d8
308 lines
12 KiB
C++
308 lines
12 KiB
C++
//===-- SparcAsmBackend.cpp - Sparc Assembler Backend ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/MC/MCAsmBackend.h"
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#include "MCTargetDesc/SparcFixupKinds.h"
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#include "MCTargetDesc/SparcMCTargetDesc.h"
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#include "llvm/MC/MCELFObjectWriter.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCFixupKindInfo.h"
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/MC/MCValue.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
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switch (Kind) {
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default:
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llvm_unreachable("Unknown fixup kind!");
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case FK_Data_1:
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case FK_Data_2:
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case FK_Data_4:
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case FK_Data_8:
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return Value;
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case Sparc::fixup_sparc_wplt30:
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case Sparc::fixup_sparc_call30:
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return (Value >> 2) & 0x3fffffff;
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case Sparc::fixup_sparc_br22:
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return (Value >> 2) & 0x3fffff;
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case Sparc::fixup_sparc_br19:
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return (Value >> 2) & 0x7ffff;
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case Sparc::fixup_sparc_br16_2:
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return (Value >> 2) & 0xc000;
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case Sparc::fixup_sparc_br16_14:
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return (Value >> 2) & 0x3fff;
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case Sparc::fixup_sparc_pc22:
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case Sparc::fixup_sparc_got22:
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case Sparc::fixup_sparc_tls_gd_hi22:
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case Sparc::fixup_sparc_tls_ldm_hi22:
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case Sparc::fixup_sparc_tls_ie_hi22:
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case Sparc::fixup_sparc_hi22:
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return (Value >> 10) & 0x3fffff;
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case Sparc::fixup_sparc_pc10:
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case Sparc::fixup_sparc_got10:
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case Sparc::fixup_sparc_tls_gd_lo10:
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case Sparc::fixup_sparc_tls_ldm_lo10:
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case Sparc::fixup_sparc_tls_ie_lo10:
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case Sparc::fixup_sparc_lo10:
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return Value & 0x3ff;
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case Sparc::fixup_sparc_tls_ldo_hix22:
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case Sparc::fixup_sparc_tls_le_hix22:
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return (~Value >> 10) & 0x3fffff;
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case Sparc::fixup_sparc_tls_ldo_lox10:
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case Sparc::fixup_sparc_tls_le_lox10:
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return (~(~Value & 0x3ff)) & 0x1fff;
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case Sparc::fixup_sparc_h44:
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return (Value >> 22) & 0x3fffff;
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case Sparc::fixup_sparc_m44:
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return (Value >> 12) & 0x3ff;
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case Sparc::fixup_sparc_l44:
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return Value & 0xfff;
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case Sparc::fixup_sparc_hh:
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return (Value >> 42) & 0x3fffff;
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case Sparc::fixup_sparc_hm:
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return (Value >> 32) & 0x3ff;
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case Sparc::fixup_sparc_tls_gd_add:
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case Sparc::fixup_sparc_tls_gd_call:
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case Sparc::fixup_sparc_tls_ldm_add:
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case Sparc::fixup_sparc_tls_ldm_call:
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case Sparc::fixup_sparc_tls_ldo_add:
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case Sparc::fixup_sparc_tls_ie_ld:
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case Sparc::fixup_sparc_tls_ie_ldx:
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case Sparc::fixup_sparc_tls_ie_add:
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return 0;
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}
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}
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namespace {
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class SparcAsmBackend : public MCAsmBackend {
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protected:
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const Target &TheTarget;
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bool IsLittleEndian;
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bool Is64Bit;
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public:
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SparcAsmBackend(const Target &T)
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: MCAsmBackend(), TheTarget(T),
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IsLittleEndian(StringRef(TheTarget.getName()) == "sparcel"),
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Is64Bit(StringRef(TheTarget.getName()) == "sparcv9") {}
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unsigned getNumFixupKinds() const override {
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return Sparc::NumTargetFixupKinds;
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}
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const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
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const static MCFixupKindInfo InfosBE[Sparc::NumTargetFixupKinds] = {
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// name offset bits flags
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{ "fixup_sparc_call30", 2, 30, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_sparc_br22", 10, 22, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_sparc_br19", 13, 19, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_sparc_br16_2", 10, 2, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_sparc_br16_14", 18, 14, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_sparc_hi22", 10, 22, 0 },
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{ "fixup_sparc_lo10", 22, 10, 0 },
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{ "fixup_sparc_h44", 10, 22, 0 },
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{ "fixup_sparc_m44", 22, 10, 0 },
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{ "fixup_sparc_l44", 20, 12, 0 },
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{ "fixup_sparc_hh", 10, 22, 0 },
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{ "fixup_sparc_hm", 22, 10, 0 },
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{ "fixup_sparc_pc22", 10, 22, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_sparc_pc10", 22, 10, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_sparc_got22", 10, 22, 0 },
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{ "fixup_sparc_got10", 22, 10, 0 },
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{ "fixup_sparc_wplt30", 2, 30, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_sparc_tls_gd_hi22", 10, 22, 0 },
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{ "fixup_sparc_tls_gd_lo10", 22, 10, 0 },
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{ "fixup_sparc_tls_gd_add", 0, 0, 0 },
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{ "fixup_sparc_tls_gd_call", 0, 0, 0 },
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{ "fixup_sparc_tls_ldm_hi22", 10, 22, 0 },
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{ "fixup_sparc_tls_ldm_lo10", 22, 10, 0 },
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{ "fixup_sparc_tls_ldm_add", 0, 0, 0 },
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{ "fixup_sparc_tls_ldm_call", 0, 0, 0 },
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{ "fixup_sparc_tls_ldo_hix22", 10, 22, 0 },
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{ "fixup_sparc_tls_ldo_lox10", 22, 10, 0 },
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{ "fixup_sparc_tls_ldo_add", 0, 0, 0 },
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{ "fixup_sparc_tls_ie_hi22", 10, 22, 0 },
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{ "fixup_sparc_tls_ie_lo10", 22, 10, 0 },
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{ "fixup_sparc_tls_ie_ld", 0, 0, 0 },
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{ "fixup_sparc_tls_ie_ldx", 0, 0, 0 },
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{ "fixup_sparc_tls_ie_add", 0, 0, 0 },
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{ "fixup_sparc_tls_le_hix22", 0, 0, 0 },
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{ "fixup_sparc_tls_le_lox10", 0, 0, 0 }
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};
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const static MCFixupKindInfo InfosLE[Sparc::NumTargetFixupKinds] = {
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// name offset bits flags
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{ "fixup_sparc_call30", 0, 30, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_sparc_br22", 0, 22, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_sparc_br19", 0, 19, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_sparc_br16_2", 20, 2, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_sparc_br16_14", 0, 14, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_sparc_hi22", 0, 22, 0 },
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{ "fixup_sparc_lo10", 0, 10, 0 },
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{ "fixup_sparc_h44", 0, 22, 0 },
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{ "fixup_sparc_m44", 0, 10, 0 },
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{ "fixup_sparc_l44", 0, 12, 0 },
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{ "fixup_sparc_hh", 0, 22, 0 },
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{ "fixup_sparc_hm", 0, 10, 0 },
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{ "fixup_sparc_pc22", 0, 22, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_sparc_pc10", 0, 10, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_sparc_got22", 0, 22, 0 },
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{ "fixup_sparc_got10", 0, 10, 0 },
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{ "fixup_sparc_wplt30", 0, 30, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_sparc_tls_gd_hi22", 0, 22, 0 },
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{ "fixup_sparc_tls_gd_lo10", 0, 10, 0 },
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{ "fixup_sparc_tls_gd_add", 0, 0, 0 },
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{ "fixup_sparc_tls_gd_call", 0, 0, 0 },
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{ "fixup_sparc_tls_ldm_hi22", 0, 22, 0 },
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{ "fixup_sparc_tls_ldm_lo10", 0, 10, 0 },
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{ "fixup_sparc_tls_ldm_add", 0, 0, 0 },
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{ "fixup_sparc_tls_ldm_call", 0, 0, 0 },
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{ "fixup_sparc_tls_ldo_hix22", 0, 22, 0 },
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{ "fixup_sparc_tls_ldo_lox10", 0, 10, 0 },
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{ "fixup_sparc_tls_ldo_add", 0, 0, 0 },
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{ "fixup_sparc_tls_ie_hi22", 0, 22, 0 },
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{ "fixup_sparc_tls_ie_lo10", 0, 10, 0 },
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{ "fixup_sparc_tls_ie_ld", 0, 0, 0 },
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{ "fixup_sparc_tls_ie_ldx", 0, 0, 0 },
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{ "fixup_sparc_tls_ie_add", 0, 0, 0 },
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{ "fixup_sparc_tls_le_hix22", 0, 0, 0 },
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{ "fixup_sparc_tls_le_lox10", 0, 0, 0 }
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};
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if (Kind < FirstTargetFixupKind)
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return MCAsmBackend::getFixupKindInfo(Kind);
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assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
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"Invalid kind!");
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if (IsLittleEndian)
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return InfosLE[Kind - FirstTargetFixupKind];
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return InfosBE[Kind - FirstTargetFixupKind];
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}
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void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,
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const MCFixup &Fixup, const MCFragment *DF,
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const MCValue &Target, uint64_t &Value,
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bool &IsResolved) override {
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switch ((Sparc::Fixups)Fixup.getKind()) {
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default: break;
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case Sparc::fixup_sparc_wplt30:
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if (Target.getSymA()->getSymbol().isTemporary())
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return;
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case Sparc::fixup_sparc_tls_gd_hi22:
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case Sparc::fixup_sparc_tls_gd_lo10:
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case Sparc::fixup_sparc_tls_gd_add:
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case Sparc::fixup_sparc_tls_gd_call:
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case Sparc::fixup_sparc_tls_ldm_hi22:
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case Sparc::fixup_sparc_tls_ldm_lo10:
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case Sparc::fixup_sparc_tls_ldm_add:
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case Sparc::fixup_sparc_tls_ldm_call:
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case Sparc::fixup_sparc_tls_ldo_hix22:
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case Sparc::fixup_sparc_tls_ldo_lox10:
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case Sparc::fixup_sparc_tls_ldo_add:
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case Sparc::fixup_sparc_tls_ie_hi22:
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case Sparc::fixup_sparc_tls_ie_lo10:
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case Sparc::fixup_sparc_tls_ie_ld:
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case Sparc::fixup_sparc_tls_ie_ldx:
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case Sparc::fixup_sparc_tls_ie_add:
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case Sparc::fixup_sparc_tls_le_hix22:
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case Sparc::fixup_sparc_tls_le_lox10: IsResolved = false; break;
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}
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}
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bool mayNeedRelaxation(const MCInst &Inst) const override {
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// FIXME.
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return false;
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}
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/// fixupNeedsRelaxation - Target specific predicate for whether a given
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/// fixup requires the associated instruction to be relaxed.
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bool fixupNeedsRelaxation(const MCFixup &Fixup,
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uint64_t Value,
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const MCRelaxableFragment *DF,
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const MCAsmLayout &Layout) const override {
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// FIXME.
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llvm_unreachable("fixupNeedsRelaxation() unimplemented");
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return false;
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}
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void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
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MCInst &Res) const override {
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// FIXME.
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llvm_unreachable("relaxInstruction() unimplemented");
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}
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bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override {
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// Cannot emit NOP with size not multiple of 32 bits.
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if (Count % 4 != 0)
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return false;
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uint64_t NumNops = Count / 4;
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for (uint64_t i = 0; i != NumNops; ++i)
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OW->write32(0x01000000);
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return true;
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}
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};
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class ELFSparcAsmBackend : public SparcAsmBackend {
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Triple::OSType OSType;
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public:
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ELFSparcAsmBackend(const Target &T, Triple::OSType OSType) :
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SparcAsmBackend(T), OSType(OSType) { }
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void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
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uint64_t Value, bool IsPCRel,
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MCContext &Ctx) const override {
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Value = adjustFixupValue(Fixup.getKind(), Value);
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if (!Value) return; // Doesn't change encoding.
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unsigned Offset = Fixup.getOffset();
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// For each byte of the fragment that the fixup touches, mask in the bits
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// from the fixup value. The Value has been "split up" into the
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// appropriate bitfields above.
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for (unsigned i = 0; i != 4; ++i) {
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unsigned Idx = IsLittleEndian ? i : 3 - i;
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Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff);
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}
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}
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MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
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uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(OSType);
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return createSparcELFObjectWriter(OS, Is64Bit, IsLittleEndian, OSABI);
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}
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};
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} // end anonymous namespace
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MCAsmBackend *llvm::createSparcAsmBackend(const Target &T,
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const MCRegisterInfo &MRI,
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const Triple &TT, StringRef CPU,
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const MCTargetOptions &Options) {
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return new ELFSparcAsmBackend(T, TT.getOS());
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}
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