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57c58d3969
Subregister definitions are considered uses for the purpose of tracking liveness of the whole register. At the same time, when calculating live interval subranges, subregister defs should not be treated as uses. Differential Revision: https://reviews.llvm.org/D24190 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280532 91177308-0d34-0410-b5e6-96231b3b80d8
56 lines
3.9 KiB
LLVM
56 lines
3.9 KiB
LLVM
; RUN: llc -march=amdgcn < %s | FileCheck %s
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; REQUIRES: asserts
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;
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; This test used to crash with the following assertion:
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; llc: include/llvm/ADT/IntervalMap.h:632: unsigned int llvm::IntervalMapImpl::LeafNode<llvm::SlotIndex, llvm::LiveInterval *, 8, llvm::IntervalMapInfo<llvm::SlotIndex> >::insertFrom(unsigned int &, unsigned int, KeyT, KeyT, ValT) [KeyT = llvm::SlotIndex, ValT = llvm::LiveInterval *, N = 8, Traits = llvm::IntervalMapInfo<llvm::SlotIndex>]: Assertion `(i == Size || Traits::stopLess(b, start(i))) && "Overlapping insert"' failed.
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;
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; This was related to incorrectly calculating subregister live ranges
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; (i.e. live interval subranges): subregister defs are not uses for that
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; purpose.
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;
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; Check for a valid output:
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; CHECK: tbuffer_store_format_x
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target triple = "amdgcn--"
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define amdgpu_gs void @main(i32 inreg %arg) #0 {
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main_body:
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%tmp = call float @llvm.SI.load.const(<16 x i8> undef, i32 20)
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%tmp1 = call float @llvm.SI.load.const(<16 x i8> undef, i32 24)
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%tmp2 = call float @llvm.SI.load.const(<16 x i8> undef, i32 48)
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%array_vector3 = insertelement <4 x float> zeroinitializer, float %tmp2, i32 3
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%array_vector5 = insertelement <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, float %tmp, i32 1
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%array_vector6 = insertelement <4 x float> %array_vector5, float undef, i32 2
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%array_vector9 = insertelement <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, float %tmp1, i32 1
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%array_vector10 = insertelement <4 x float> %array_vector9, float 0.000000e+00, i32 2
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%array_vector11 = insertelement <4 x float> %array_vector10, float undef, i32 3
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%tmp3 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> undef, i32 undef, i32 4864, i32 0, i32 1, i32 0, i32 1, i32 0, i32 0)
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call void @llvm.SI.tbuffer.store.i32(<16 x i8> undef, i32 %tmp3, i32 1, i32 36, i32 %arg, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
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%bc = bitcast <4 x float> %array_vector3 to <4 x i32>
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%tmp4 = extractelement <4 x i32> %bc, i32 undef
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call void @llvm.SI.tbuffer.store.i32(<16 x i8> undef, i32 %tmp4, i32 1, i32 48, i32 %arg, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
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%bc49 = bitcast <4 x float> %array_vector11 to <4 x i32>
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%tmp5 = extractelement <4 x i32> %bc49, i32 undef
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call void @llvm.SI.tbuffer.store.i32(<16 x i8> undef, i32 %tmp5, i32 1, i32 72, i32 %arg, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
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%array_vector21 = insertelement <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, float %tmp, i32 1
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%array_vector22 = insertelement <4 x float> %array_vector21, float undef, i32 2
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%array_vector23 = insertelement <4 x float> %array_vector22, float undef, i32 3
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call void @llvm.SI.tbuffer.store.i32(<16 x i8> undef, i32 undef, i32 1, i32 28, i32 %arg, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
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%bc52 = bitcast <4 x float> %array_vector23 to <4 x i32>
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%tmp6 = extractelement <4 x i32> %bc52, i32 undef
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call void @llvm.SI.tbuffer.store.i32(<16 x i8> undef, i32 %tmp6, i32 1, i32 64, i32 %arg, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
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call void @llvm.SI.tbuffer.store.i32(<16 x i8> undef, i32 undef, i32 1, i32 20, i32 %arg, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
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call void @llvm.SI.tbuffer.store.i32(<16 x i8> undef, i32 undef, i32 1, i32 56, i32 %arg, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
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call void @llvm.SI.tbuffer.store.i32(<16 x i8> undef, i32 undef, i32 1, i32 92, i32 %arg, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
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ret void
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}
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declare float @llvm.SI.load.const(<16 x i8>, i32) #1
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declare i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #2
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declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) #3
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attributes #0 = { nounwind "target-cpu"="tonga" }
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attributes #1 = { nounwind readnone }
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attributes #2 = { nounwind readonly }
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attributes #3 = { nounwind }
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