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Merge the tail block into the loop in cases where the main loop body exits early, subject to profitability constraints. This will coalesce the loop body into fewer blocks. For example: loop: loop: // loop body // loop body if (...) jump exit --> // more body more: if (...) jump exit // more body jump loop jump loop git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297033 91177308-0d34-0410-b5e6-96231b3b80d8
65 lines
1.7 KiB
LLVM
65 lines
1.7 KiB
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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; CHECK: .LJTI
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; CHECK-DAG: r[[REG:[0-9]+]] = memw(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+<<#[0-9]+}})
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; CHECK-DAG: jumpr r[[REG]]
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define void @main() #0 {
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entry:
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%ret = alloca i32, align 4
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br label %while.body
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while.body:
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%ret.0.load17 = load volatile i32, i32* %ret, align 4
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switch i32 %ret.0.load17, label %label6 [
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i32 0, label %label0
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i32 1, label %label1
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i32 2, label %label2
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i32 3, label %label3
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i32 4, label %label4
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i32 5, label %label5
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]
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label0:
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%ret.0.load18 = load volatile i32, i32* %ret, align 4
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%inc = add nsw i32 %ret.0.load18, 1
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store volatile i32 %inc, i32* %ret, align 4
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br label %while.body
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label1:
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%ret.0.load19 = load volatile i32, i32* %ret, align 4
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%inc2 = add nsw i32 %ret.0.load19, 1
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store volatile i32 %inc2, i32* %ret, align 4
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br label %while.body
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label2:
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%ret.0.load20 = load volatile i32, i32* %ret, align 4
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%inc4 = add nsw i32 %ret.0.load20, 1
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store volatile i32 %inc4, i32* %ret, align 4
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br label %while.body
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label3:
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%ret.0.load21 = load volatile i32, i32* %ret, align 4
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%inc6 = add nsw i32 %ret.0.load21, 1
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store volatile i32 %inc6, i32* %ret, align 4
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br label %while.body
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label4:
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%ret.0.load22 = load volatile i32, i32* %ret, align 4
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%inc8 = add nsw i32 %ret.0.load22, 1
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store volatile i32 %inc8, i32* %ret, align 4
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br label %while.body
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label5:
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%ret.0.load23 = load volatile i32, i32* %ret, align 4
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%inc10 = add nsw i32 %ret.0.load23, 1
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store volatile i32 %inc10, i32* %ret, align 4
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br label %while.body
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label6:
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store volatile i32 0, i32* %ret, align 4
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br label %while.body
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}
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attributes #0 = { noreturn nounwind "target-cpu"="hexagonv4" }
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