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On Hexagon, values of type i1 are passed in registers of type i32, even though i1 is not a legal value for these registers. This is a special case and needs special handling to maintain consistency of the lowering information. This fixes PR32089. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296645 91177308-0d34-0410-b5e6-96231b3b80d8
7 lines
109 B
LLVM
7 lines
109 B
LLVM
; RUN: llc -march=hexagon -debug-only=isel < %s
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; REQUIRES: asserts
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define void @g(i1 %cond) {
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ret void
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}
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