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d8c5ecbd82
This patch fixes the non-determinism caused due to iterating SmallPtrSet's which was uncovered due to the experimental "reverse iteration order " patch: https://reviews.llvm.org/D26718 The following unit tests failed because of the undefined order of iteration. LLVM :: Transforms/Util/MemorySSA/cyclicphi.ll LLVM :: Transforms/Util/MemorySSA/many-dom-backedge.ll LLVM :: Transforms/Util/MemorySSA/many-doms.ll LLVM :: Transforms/Util/MemorySSA/phi-translation.ll Reviewers: dberlin, mgrang Subscribers: dberlin, llvm-commits, david2050 Differential Revision: https://reviews.llvm.org/D26704 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287563 91177308-0d34-0410-b5e6-96231b3b80d8
78 lines
1.9 KiB
LLVM
78 lines
1.9 KiB
LLVM
; RUN: opt -basicaa -print-memoryssa -verify-memoryssa -analyze < %s 2>&1 | FileCheck %s
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; RUN: opt -aa-pipeline=basic-aa -passes='print<memoryssa>,verify<memoryssa>' -disable-output < %s 2>&1 | FileCheck %s
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;
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; many-dom.ll, with an added back-edge back into the switch.
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; Because people love their gotos.
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declare i1 @getBool() readnone
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define i32 @foo(i32* %p) {
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entry:
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br label %loopbegin
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loopbegin:
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; CHECK: 8 = MemoryPhi({entry,liveOnEntry},{sw.epilog,6})
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; CHECK-NEXT: %n =
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%n = phi i32 [ 0, %entry ], [ %1, %sw.epilog ]
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%m = alloca i32, align 4
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switch i32 %n, label %sw.default [
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i32 0, label %sw.bb
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i32 1, label %sw.bb1
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i32 2, label %sw.bb2
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i32 3, label %sw.bb3
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]
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sw.bb:
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; CHECK: 1 = MemoryDef(8)
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; CHECK-NEXT: store i32 1
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store i32 1, i32* %m, align 4
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br label %sw.epilog
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sw.bb1:
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; CHECK: 2 = MemoryDef(8)
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; CHECK-NEXT: store i32 2
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store i32 2, i32* %m, align 4
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br label %sw.epilog
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sw.bb2:
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; CHECK: 3 = MemoryDef(8)
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; CHECK-NEXT: store i32 3
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store i32 3, i32* %m, align 4
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br label %sw.epilog
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sw.bb3:
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; CHECK: 9 = MemoryPhi({loopbegin,8},{sw.almostexit,6})
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; CHECK: 4 = MemoryDef(9)
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; CHECK-NEXT: store i32 4
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store i32 4, i32* %m, align 4
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br label %sw.epilog
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sw.default:
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; CHECK: 5 = MemoryDef(8)
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; CHECK-NEXT: store i32 5
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store i32 5, i32* %m, align 4
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br label %sw.epilog
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sw.epilog:
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; CHECK: 10 = MemoryPhi({sw.default,5},{sw.bb3,4},{sw.bb,1},{sw.bb1,2},{sw.bb2,3})
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; CHECK-NEXT: MemoryUse(10)
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; CHECK-NEXT: %0 =
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%0 = load i32, i32* %m, align 4
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; CHECK: 6 = MemoryDef(10)
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; CHECK-NEXT: %1 =
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%1 = load volatile i32, i32* %p, align 4
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%2 = icmp eq i32 %0, %1
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br i1 %2, label %sw.almostexit, label %loopbegin
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sw.almostexit:
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%3 = icmp eq i32 0, %1
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br i1 %3, label %exit, label %sw.bb3
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exit:
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; CHECK: 7 = MemoryDef(6)
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; CHECK-NEXT: %4 = load volatile i32
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%4 = load volatile i32, i32* %p, align 4
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%5 = add i32 %4, %1
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ret i32 %5
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}
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