Guozhi Wei d3fe6038ab [PPC] Change the register constraint of the first source operand of instruction mtvsrdd to g8rc_nox0 ... According to Power ISA V3.0 document, the first source operand of mtvsrdd is constant 0 if r0 is specified. So the corresponding register constraint should be g8rc_nox0. This bug caused wrong output generated by 401.bzip2 when -mcpu=power9 and fdo are specified. Differential Revision: https://reviews.llvm.org/D32880 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302834 91177308-0d34-0410-b5e6-96231b3b80d8		2017-05-11 22:17:35 +00:00
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AArch64	[AArch64] armv8-A doesn't have CRC.	2017-05-03 20:33:52 +00:00
AMDGPU	AMDGPU: Remove tfe bit from flat instruction definitions	2017-05-11 17:38:33 +00:00
ARM	[ARM] Saturation instructions are DSP-only	2016-07-25 22:25:25 +00:00
Hexagon	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
Lanai
Mips	[mips] Correct c.cond.fmt instruction definition.	2017-01-16 13:55:58 +00:00
PowerPC	[PPC] Change the register constraint of the first source operand of instruction mtvsrdd to g8rc_nox0	2017-05-11 22:17:35 +00:00
Sparc
SystemZ	[SystemZ] Add miscellaneous instructions	2017-05-10 14:20:15 +00:00
X86	[X86][LWP] Add llvm support for LWP instructions (reapplied).	2017-05-03 15:51:39 +00:00
XCore