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4d28d7365a
individual cases, while hard coding less about registers in use. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134330 91177308-0d34-0410-b5e6-96231b3b80d8
73 lines
1.7 KiB
LLVM
73 lines
1.7 KiB
LLVM
; RUN: llc < %s | FileCheck %s
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; rdar://5671654
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; The loads should fold into the testl instructions, no matter how
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; the inputs are commuted.
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
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target triple = "x86_64-apple-darwin7"
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define i32 @test(i32* %P, i32* %G) nounwind {
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; CHECK: test:
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; CHECK-NOT: ret
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; CHECK: testl (%{{.*}}), %{{.*}}
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; CHECK: ret
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entry:
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%0 = load i32* %P, align 4 ; <i32> [#uses=3]
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%1 = load i32* %G, align 4 ; <i32> [#uses=1]
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%2 = and i32 %1, %0 ; <i32> [#uses=1]
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%3 = icmp eq i32 %2, 0 ; <i1> [#uses=1]
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br i1 %3, label %bb1, label %bb
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bb: ; preds = %entry
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%4 = tail call i32 @bar() nounwind ; <i32> [#uses=0]
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ret i32 %0
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bb1: ; preds = %entry
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ret i32 %0
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}
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define i32 @test2(i32* %P, i32* %G) nounwind {
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; CHECK: test2:
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; CHECK-NOT: ret
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; CHECK: testl (%{{.*}}), %{{.*}}
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; CHECK: ret
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entry:
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%0 = load i32* %P, align 4 ; <i32> [#uses=3]
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%1 = load i32* %G, align 4 ; <i32> [#uses=1]
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%2 = and i32 %0, %1 ; <i32> [#uses=1]
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%3 = icmp eq i32 %2, 0 ; <i1> [#uses=1]
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br i1 %3, label %bb1, label %bb
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bb: ; preds = %entry
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%4 = tail call i32 @bar() nounwind ; <i32> [#uses=0]
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ret i32 %0
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bb1: ; preds = %entry
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ret i32 %0
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}
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define i32 @test3(i32* %P, i32* %G) nounwind {
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; CHECK: test3:
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; CHECK-NOT: ret
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; CHECK: testl (%{{.*}}), %{{.*}}
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; CHECK: ret
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entry:
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%0 = load i32* %P, align 4 ; <i32> [#uses=3]
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%1 = load i32* %G, align 4 ; <i32> [#uses=1]
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%2 = and i32 %0, %1 ; <i32> [#uses=1]
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%3 = icmp eq i32 %2, 0 ; <i1> [#uses=1]
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br i1 %3, label %bb1, label %bb
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bb: ; preds = %entry
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%4 = tail call i32 @bar() nounwind ; <i32> [#uses=0]
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ret i32 %1
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bb1: ; preds = %entry
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ret i32 %1
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}
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declare i32 @bar()
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