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https://github.com/RPCS3/llvm.git
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793ce99ea7
As on other hosts, the CPU identification instruction is priveleged, so we need to look through /proc/cpuinfo. I copied the PowerPC way of handling "generic". Several tests were implicitly assuming z10 and so failed on z196. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193742 91177308-0d34-0410-b5e6-96231b3b80d8
394 lines
12 KiB
LLVM
394 lines
12 KiB
LLVM
; Test moves between FPRs and GPRs. The 32-bit cases test the z10
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; implementation, which has no high-word support.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
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declare i64 @foo()
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declare double @bar()
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@dptr = external global double
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@iptr = external global i64
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; Test 32-bit moves from GPRs to FPRs. The GPR must be moved into the high
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; 32 bits of the FPR.
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define float @f1(i32 %a) {
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; CHECK-LABEL: f1:
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; CHECK: sllg [[REGISTER:%r[0-5]]], %r2, 32
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; CHECK: ldgr %f0, [[REGISTER]]
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%res = bitcast i32 %a to float
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ret float %res
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}
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; Like f1, but create a situation where the shift can be folded with
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; surrounding code.
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define float @f2(i64 %big) {
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; CHECK-LABEL: f2:
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; CHECK: risbg [[REGISTER:%r[0-5]]], %r2, 0, 159, 31
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; CHECK: ldgr %f0, [[REGISTER]]
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%shift = lshr i64 %big, 1
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%a = trunc i64 %shift to i32
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%res = bitcast i32 %a to float
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ret float %res
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}
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; Another example of the same thing.
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define float @f3(i64 %big) {
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; CHECK-LABEL: f3:
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; CHECK: risbg [[REGISTER:%r[0-5]]], %r2, 0, 159, 2
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; CHECK: ldgr %f0, [[REGISTER]]
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%shift = ashr i64 %big, 30
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%a = trunc i64 %shift to i32
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%res = bitcast i32 %a to float
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ret float %res
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}
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; Like f1, but the value to transfer is already in the high 32 bits.
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define float @f4(i64 %big) {
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; CHECK-LABEL: f4:
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; CHECK-NOT: %r2
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; CHECK: nilf %r2, 0
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; CHECK-NOT: %r2
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; CHECK: ldgr %f0, %r2
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%shift = ashr i64 %big, 32
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%a = trunc i64 %shift to i32
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%res = bitcast i32 %a to float
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ret float %res
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}
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; Test 64-bit moves from GPRs to FPRs.
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define double @f5(i64 %a) {
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; CHECK-LABEL: f5:
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; CHECK: ldgr %f0, %r2
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%res = bitcast i64 %a to double
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ret double %res
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}
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; Test 128-bit moves from GPRs to FPRs. i128 isn't a legitimate type,
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; so this goes through memory.
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define void @f6(fp128 *%a, i128 *%b) {
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; CHECK-LABEL: f6:
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; CHECK: lg
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; CHECK: lg
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; CHECK: stg
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; CHECK: stg
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; CHECK: br %r14
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%val = load i128 *%b
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%res = bitcast i128 %val to fp128
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store fp128 %res, fp128 *%a
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ret void
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}
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; Test 32-bit moves from FPRs to GPRs. The high 32 bits of the FPR should
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; be moved into the low 32 bits of the GPR.
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define i32 @f7(float %a) {
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; CHECK-LABEL: f7:
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; CHECK: lgdr [[REGISTER:%r[0-5]]], %f0
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; CHECK: srlg %r2, [[REGISTER]], 32
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%res = bitcast float %a to i32
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ret i32 %res
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}
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; Test 64-bit moves from FPRs to GPRs.
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define i64 @f8(double %a) {
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; CHECK-LABEL: f8:
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; CHECK: lgdr %r2, %f0
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%res = bitcast double %a to i64
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ret i64 %res
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}
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; Test 128-bit moves from FPRs to GPRs, with the same restriction as f6.
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define void @f9(fp128 *%a, i128 *%b) {
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; CHECK-LABEL: f9:
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; CHECK: ld
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; CHECK: ld
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; CHECK: std
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; CHECK: std
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%val = load fp128 *%a
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%res = bitcast fp128 %val to i128
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store i128 %res, i128 *%b
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ret void
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}
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; Test cases where the destination of an LGDR needs to be spilled.
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; We shouldn't have any integer stack stores or floating-point loads.
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define void @f10(double %extra) {
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; CHECK-LABEL: f10:
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; CHECK: dptr
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; CHECK-NOT: stg {{.*}}(%r15)
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; CHECK: %loop
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; CHECK-NOT: ld {{.*}}(%r15)
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; CHECK: %exit
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; CHECK: br %r14
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entry:
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%double0 = load volatile double *@dptr
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%biased0 = fadd double %double0, %extra
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%int0 = bitcast double %biased0 to i64
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%double1 = load volatile double *@dptr
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%biased1 = fadd double %double1, %extra
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%int1 = bitcast double %biased1 to i64
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%double2 = load volatile double *@dptr
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%biased2 = fadd double %double2, %extra
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%int2 = bitcast double %biased2 to i64
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%double3 = load volatile double *@dptr
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%biased3 = fadd double %double3, %extra
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%int3 = bitcast double %biased3 to i64
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%double4 = load volatile double *@dptr
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%biased4 = fadd double %double4, %extra
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%int4 = bitcast double %biased4 to i64
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%double5 = load volatile double *@dptr
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%biased5 = fadd double %double5, %extra
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%int5 = bitcast double %biased5 to i64
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%double6 = load volatile double *@dptr
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%biased6 = fadd double %double6, %extra
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%int6 = bitcast double %biased6 to i64
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%double7 = load volatile double *@dptr
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%biased7 = fadd double %double7, %extra
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%int7 = bitcast double %biased7 to i64
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%double8 = load volatile double *@dptr
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%biased8 = fadd double %double8, %extra
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%int8 = bitcast double %biased8 to i64
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%double9 = load volatile double *@dptr
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%biased9 = fadd double %double9, %extra
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%int9 = bitcast double %biased9 to i64
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br label %loop
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loop:
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%start = call i64 @foo()
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%or0 = or i64 %start, %int0
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%or1 = or i64 %or0, %int1
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%or2 = or i64 %or1, %int2
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%or3 = or i64 %or2, %int3
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%or4 = or i64 %or3, %int4
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%or5 = or i64 %or4, %int5
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%or6 = or i64 %or5, %int6
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%or7 = or i64 %or6, %int7
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%or8 = or i64 %or7, %int8
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%or9 = or i64 %or8, %int9
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store i64 %or9, i64 *@iptr
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%cont = icmp ne i64 %start, 1
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br i1 %cont, label %loop, label %exit
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exit:
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ret void
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}
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; ...likewise LDGR, with the requirements the other way around.
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define void @f11(i64 %mask) {
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; CHECK-LABEL: f11:
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; CHECK: iptr
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; CHECK-NOT: std {{.*}}(%r15)
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; CHECK: %loop
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; CHECK-NOT: lg {{.*}}(%r15)
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; CHECK: %exit
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; CHECK: br %r14
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entry:
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%int0 = load volatile i64 *@iptr
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%masked0 = and i64 %int0, %mask
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%double0 = bitcast i64 %masked0 to double
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%int1 = load volatile i64 *@iptr
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%masked1 = and i64 %int1, %mask
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%double1 = bitcast i64 %masked1 to double
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%int2 = load volatile i64 *@iptr
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%masked2 = and i64 %int2, %mask
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%double2 = bitcast i64 %masked2 to double
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%int3 = load volatile i64 *@iptr
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%masked3 = and i64 %int3, %mask
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%double3 = bitcast i64 %masked3 to double
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%int4 = load volatile i64 *@iptr
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%masked4 = and i64 %int4, %mask
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%double4 = bitcast i64 %masked4 to double
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%int5 = load volatile i64 *@iptr
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%masked5 = and i64 %int5, %mask
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%double5 = bitcast i64 %masked5 to double
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%int6 = load volatile i64 *@iptr
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%masked6 = and i64 %int6, %mask
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%double6 = bitcast i64 %masked6 to double
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%int7 = load volatile i64 *@iptr
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%masked7 = and i64 %int7, %mask
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%double7 = bitcast i64 %masked7 to double
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%int8 = load volatile i64 *@iptr
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%masked8 = and i64 %int8, %mask
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%double8 = bitcast i64 %masked8 to double
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%int9 = load volatile i64 *@iptr
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%masked9 = and i64 %int9, %mask
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%double9 = bitcast i64 %masked9 to double
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br label %loop
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loop:
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%start = call double @bar()
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%add0 = fadd double %start, %double0
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%add1 = fadd double %add0, %double1
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%add2 = fadd double %add1, %double2
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%add3 = fadd double %add2, %double3
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%add4 = fadd double %add3, %double4
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%add5 = fadd double %add4, %double5
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%add6 = fadd double %add5, %double6
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%add7 = fadd double %add6, %double7
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%add8 = fadd double %add7, %double8
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%add9 = fadd double %add8, %double9
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store double %add9, double *@dptr
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%cont = fcmp one double %start, 1.0
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br i1 %cont, label %loop, label %exit
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exit:
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ret void
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}
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; Test cases where the source of an LDGR needs to be spilled.
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; We shouldn't have any integer stack stores or floating-point loads.
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define void @f12() {
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; CHECK-LABEL: f12:
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; CHECK: %loop
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; CHECK-NOT: std {{.*}}(%r15)
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; CHECK: %exit
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; CHECK: foo@PLT
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; CHECK-NOT: lg {{.*}}(%r15)
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; CHECK: foo@PLT
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; CHECK: br %r14
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entry:
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br label %loop
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loop:
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%int0 = phi i64 [ 0, %entry ], [ %add0, %loop ]
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%int1 = phi i64 [ 0, %entry ], [ %add1, %loop ]
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%int2 = phi i64 [ 0, %entry ], [ %add2, %loop ]
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%int3 = phi i64 [ 0, %entry ], [ %add3, %loop ]
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%int4 = phi i64 [ 0, %entry ], [ %add4, %loop ]
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%int5 = phi i64 [ 0, %entry ], [ %add5, %loop ]
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%int6 = phi i64 [ 0, %entry ], [ %add6, %loop ]
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%int7 = phi i64 [ 0, %entry ], [ %add7, %loop ]
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%int8 = phi i64 [ 0, %entry ], [ %add8, %loop ]
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%int9 = phi i64 [ 0, %entry ], [ %add9, %loop ]
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%bias = call i64 @foo()
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%add0 = add i64 %int0, %bias
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%add1 = add i64 %int1, %bias
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%add2 = add i64 %int2, %bias
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%add3 = add i64 %int3, %bias
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%add4 = add i64 %int4, %bias
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%add5 = add i64 %int5, %bias
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%add6 = add i64 %int6, %bias
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%add7 = add i64 %int7, %bias
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%add8 = add i64 %int8, %bias
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%add9 = add i64 %int9, %bias
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%cont = icmp ne i64 %bias, 1
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br i1 %cont, label %loop, label %exit
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exit:
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%unused1 = call i64 @foo()
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%factor = load volatile double *@dptr
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%conv0 = bitcast i64 %add0 to double
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%mul0 = fmul double %conv0, %factor
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store volatile double %mul0, double *@dptr
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%conv1 = bitcast i64 %add1 to double
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%mul1 = fmul double %conv1, %factor
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store volatile double %mul1, double *@dptr
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%conv2 = bitcast i64 %add2 to double
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%mul2 = fmul double %conv2, %factor
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store volatile double %mul2, double *@dptr
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%conv3 = bitcast i64 %add3 to double
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%mul3 = fmul double %conv3, %factor
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store volatile double %mul3, double *@dptr
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%conv4 = bitcast i64 %add4 to double
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%mul4 = fmul double %conv4, %factor
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store volatile double %mul4, double *@dptr
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%conv5 = bitcast i64 %add5 to double
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%mul5 = fmul double %conv5, %factor
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store volatile double %mul5, double *@dptr
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%conv6 = bitcast i64 %add6 to double
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%mul6 = fmul double %conv6, %factor
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store volatile double %mul6, double *@dptr
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%conv7 = bitcast i64 %add7 to double
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%mul7 = fmul double %conv7, %factor
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store volatile double %mul7, double *@dptr
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%conv8 = bitcast i64 %add8 to double
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%mul8 = fmul double %conv8, %factor
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store volatile double %mul8, double *@dptr
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%conv9 = bitcast i64 %add9 to double
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%mul9 = fmul double %conv9, %factor
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store volatile double %mul9, double *@dptr
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%unused2 = call i64 @foo()
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ret void
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}
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; ...likewise LGDR, with the requirements the other way around.
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define void @f13() {
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; CHECK-LABEL: f13:
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; CHECK: %loop
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; CHECK-NOT: stg {{.*}}(%r15)
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; CHECK: %exit
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; CHECK: foo@PLT
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; CHECK-NOT: ld {{.*}}(%r15)
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; CHECK: foo@PLT
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; CHECK: br %r14
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entry:
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br label %loop
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loop:
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%double0 = phi double [ 1.0, %entry ], [ %mul0, %loop ]
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%double1 = phi double [ 1.0, %entry ], [ %mul1, %loop ]
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%double2 = phi double [ 1.0, %entry ], [ %mul2, %loop ]
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%double3 = phi double [ 1.0, %entry ], [ %mul3, %loop ]
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%double4 = phi double [ 1.0, %entry ], [ %mul4, %loop ]
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%double5 = phi double [ 1.0, %entry ], [ %mul5, %loop ]
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%double6 = phi double [ 1.0, %entry ], [ %mul6, %loop ]
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%double7 = phi double [ 1.0, %entry ], [ %mul7, %loop ]
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%double8 = phi double [ 1.0, %entry ], [ %mul8, %loop ]
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%double9 = phi double [ 1.0, %entry ], [ %mul9, %loop ]
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%factor = call double @bar()
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%mul0 = fmul double %double0, %factor
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%mul1 = fmul double %double1, %factor
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%mul2 = fmul double %double2, %factor
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%mul3 = fmul double %double3, %factor
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%mul4 = fmul double %double4, %factor
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%mul5 = fmul double %double5, %factor
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%mul6 = fmul double %double6, %factor
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%mul7 = fmul double %double7, %factor
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%mul8 = fmul double %double8, %factor
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%mul9 = fmul double %double9, %factor
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%cont = fcmp one double %factor, 1.0
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br i1 %cont, label %loop, label %exit
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exit:
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%unused1 = call i64 @foo()
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%bias = load volatile i64 *@iptr
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%conv0 = bitcast double %mul0 to i64
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%add0 = add i64 %conv0, %bias
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store volatile i64 %add0, i64 *@iptr
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%conv1 = bitcast double %mul1 to i64
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%add1 = add i64 %conv1, %bias
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store volatile i64 %add1, i64 *@iptr
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%conv2 = bitcast double %mul2 to i64
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%add2 = add i64 %conv2, %bias
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store volatile i64 %add2, i64 *@iptr
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%conv3 = bitcast double %mul3 to i64
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%add3 = add i64 %conv3, %bias
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store volatile i64 %add3, i64 *@iptr
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%conv4 = bitcast double %mul4 to i64
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%add4 = add i64 %conv4, %bias
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store volatile i64 %add4, i64 *@iptr
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%conv5 = bitcast double %mul5 to i64
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%add5 = add i64 %conv5, %bias
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store volatile i64 %add5, i64 *@iptr
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%conv6 = bitcast double %mul6 to i64
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%add6 = add i64 %conv6, %bias
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store volatile i64 %add6, i64 *@iptr
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%conv7 = bitcast double %mul7 to i64
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%add7 = add i64 %conv7, %bias
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store volatile i64 %add7, i64 *@iptr
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%conv8 = bitcast double %mul8 to i64
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%add8 = add i64 %conv8, %bias
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store volatile i64 %add8, i64 *@iptr
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%conv9 = bitcast double %mul9 to i64
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%add9 = add i64 %conv9, %bias
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store volatile i64 %add9, i64 *@iptr
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%unused2 = call i64 @foo()
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ret void
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}
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