llvm/test at 52981c4b6016d9f0e295e0771ec0a50dd073b4b3 - llvm

RPCS3/llvm

mirror of https://github.com/RPCS3/llvm.git synced 2025-02-06 02:29:51 +00:00

History

Elena Demikhovsky 52981c4b60 I optimized the following patterns:

sext <4 x i1> to <4 x i64>
 sext <4 x i8> to <4 x i64>
 sext <4 x i16> to <4 x i64>
 
I'm running Combine on SIGN_EXTEND_IN_REG and revert SEXT patterns:
 (sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) -> (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
 
 The sext_in_reg (v4i32 x) may be lowered to shl+sar operations.
 The "sar" does not exist on 64-bit operation, so lowering sext_in_reg (v4i64 x) has no vector solution.

I also added a cost of this operations to the AVX costs table.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175619 91177308-0d34-0410-b5e6-96231b3b80d8

2013-02-20 12:42:54 +00:00

Analysis

I optimized the following patterns:

2013-02-20 12:42:54 +00:00

Archive

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Assembler

Modify the LLVM assembly output so that it uses references to represent function attributes.

2013-02-20 07:21:42 +00:00

Bindings/Ocaml

Use the attribute group reference instead of the attribute directly.

2013-02-20 07:48:23 +00:00