Robert Lytton 546cfbfd0a XCore target: remove incorrect DebugLoc entries from prologue ...

Summary: This was causing the prologue_end to be incorrectly positioned.

Differential Revision: http://reviews.llvm.org/D4122

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212318 91177308-0d34-0410-b5e6-96231b3b80d8

2014-07-04 06:38:22 +00:00

..

AArch64

[aarch64] Add a test that should have been in r212242 but I forgot to

2014-07-03 02:12:26 +00:00

ARM

[ARM] Implement ISB memory barrier intrinsic

2014-07-03 16:00:41 +00:00

CPP

IR: add "cmpxchg weak" variant to support permitted failure.

2014-06-13 14:24:07 +00:00

Generic

Add a new attribute called 'jumptable' that creates jump-instruction tables for functions marked with this attribute.

2014-06-05 19:29:43 +00:00

Hexagon

Reduce verbiage of lit.local.cfg files

2014-06-09 22:42:55 +00:00

Inputs

Debug Info: update testing cases to specify the debug info version number.

2013-11-22 21:49:45 +00:00

Mips

Print a=b as an assignment.

2014-06-24 22:45:16 +00:00

MSP430

Reduce verbiage of lit.local.cfg files

2014-06-09 22:42:55 +00:00

NVPTX

[NVPTX] Add reflect intrinsic (better than matching by function name)

2014-06-27 18:36:11 +00:00

PowerPC

Fix ppcf128 component access on little-endian systems

2014-07-03 15:06:47 +00:00

R600

R600: Promote i64 loads to v2i32

2014-07-02 20:53:54 +00:00

SPARC

IR: add "cmpxchg weak" variant to support permitted failure.

2014-06-13 14:24:07 +00:00

SystemZ

IR: add "cmpxchg weak" variant to support permitted failure.

2014-06-13 14:24:07 +00:00

Thumb

ARM: Fix fastcc calling convention for Thumb1

2014-06-13 08:33:03 +00:00

Thumb2

ARM: Fix TPsoft for Thumb mode

2014-06-24 15:45:59 +00:00

X86

Temporarily revert "Don't try to construct debug LexicalScopes hierarchy for functions that do not have top level debug information." as it appears to be breaking some LTO constructs.

2014-07-03 22:24:54 +00:00

XCore

XCore target: remove incorrect DebugLoc entries from prologue

2014-07-04 06:38:22 +00:00