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llvm/lib/Target/R600/SIInstrInfo.td
Tom Stellard 163d8ce61f R600/SI: Refactor VOP3 instruction definitions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213571 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-21 17:44:29 +00:00

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//===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
// Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
// in AMDGPUMCInstLower.h
def SISubtarget {
int NONE = -1;
int SI = 0;
}
//===----------------------------------------------------------------------===//
// SI DAG Nodes
//===----------------------------------------------------------------------===//
def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
[SDNPMayLoad, SDNPMemOperand]
>;
def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
SDTypeProfile<0, 13,
[SDTCisVT<0, v4i32>, // rsrc(SGPR)
SDTCisVT<1, iAny>, // vdata(VGPR)
SDTCisVT<2, i32>, // num_channels(imm)
SDTCisVT<3, i32>, // vaddr(VGPR)
SDTCisVT<4, i32>, // soffset(SGPR)
SDTCisVT<5, i32>, // inst_offset(imm)
SDTCisVT<6, i32>, // dfmt(imm)
SDTCisVT<7, i32>, // nfmt(imm)
SDTCisVT<8, i32>, // offen(imm)
SDTCisVT<9, i32>, // idxen(imm)
SDTCisVT<10, i32>, // glc(imm)
SDTCisVT<11, i32>, // slc(imm)
SDTCisVT<12, i32> // tfe(imm)
]>,
[SDNPMayStore, SDNPMemOperand, SDNPHasChain]
>;
def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
SDTCisVT<3, i32>]>
>;
class SDSample<string opcode> : SDNode <opcode,
SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
>;
def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
def SIconstdata_ptr : SDNode<
"AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
>;
// Transformation function, extract the lower 32bit of a 64bit immediate
def LO32 : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
}]>;
def LO32f : SDNodeXForm<fpimm, [{
APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
}]>;
// Transformation function, extract the upper 32bit of a 64bit immediate
def HI32 : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
}]>;
def HI32f : SDNodeXForm<fpimm, [{
APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
}]>;
def IMM8bitDWORD : PatLeaf <(imm),
[{return (N->getZExtValue() & ~0x3FC) == 0;}]
>;
def as_dword_i32imm : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
}]>;
def as_i1imm : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
}]>;
def as_i8imm : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
}]>;
def as_i16imm : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
}]>;
def as_i32imm: SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
}]>;
def IMM8bit : PatLeaf <(imm),
[{return isUInt<8>(N->getZExtValue());}]
>;
def IMM12bit : PatLeaf <(imm),
[{return isUInt<12>(N->getZExtValue());}]
>;
def IMM16bit : PatLeaf <(imm),
[{return isUInt<16>(N->getZExtValue());}]
>;
def IMM32bit : PatLeaf <(imm),
[{return isUInt<32>(N->getZExtValue());}]
>;
def mubuf_vaddr_offset : PatFrag<
(ops node:$ptr, node:$offset, node:$imm_offset),
(add (add node:$ptr, node:$offset), node:$imm_offset)
>;
class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
return isInlineImmediate(N);
}]>;
class SGPRImm <dag frag> : PatLeaf<frag, [{
if (TM.getSubtarget<AMDGPUSubtarget>().getGeneration() <
AMDGPUSubtarget::SOUTHERN_ISLANDS) {
return false;
}
const SIRegisterInfo *SIRI =
static_cast<const SIRegisterInfo*>(TM.getRegisterInfo());
for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
U != E; ++U) {
if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
return true;
}
}
return false;
}]>;
//===----------------------------------------------------------------------===//
// Custom Operands
//===----------------------------------------------------------------------===//
def FRAMEri32 : Operand<iPTR> {
let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
}
def sopp_brtarget : Operand<OtherVT> {
let EncoderMethod = "getSOPPBrEncoding";
let OperandType = "OPERAND_PCREL";
}
//===----------------------------------------------------------------------===//
// Complex patterns
//===----------------------------------------------------------------------===//
def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
def MUBUFAddr64 : ComplexPattern<i64, 3, "SelectMUBUFAddr64">;
def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
//===----------------------------------------------------------------------===//
// SI assembler operands
//===----------------------------------------------------------------------===//
def SIOperand {
int ZERO = 0x80;
int VCC = 0x6A;
}
include "SIInstrFormats.td"
//===----------------------------------------------------------------------===//
//
// SI Instruction multiclass helpers.
//
// Instructions with _32 take 32-bit operands.
// Instructions with _64 take 64-bit operands.
//
// VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
// encoding is the standard encoding, but instruction that make use of
// any of the instruction modifiers must use the 64-bit encoding.
//
// Instructions with _e32 use the 32-bit encoding.
// Instructions with _e64 use the 64-bit encoding.
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Scalar classes
//===----------------------------------------------------------------------===//
class SOP1_32 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
op, (outs SReg_32:$dst), (ins SSrc_32:$src0),
opName#" $dst, $src0", pattern
>;
class SOP1_64 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
op, (outs SReg_64:$dst), (ins SSrc_64:$src0),
opName#" $dst, $src0", pattern
>;
// 64-bit input, 32-bit output.
class SOP1_32_64 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
op, (outs SReg_32:$dst), (ins SSrc_64:$src0),
opName#" $dst, $src0", pattern
>;
class SOP2_32 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
op, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
opName#" $dst, $src0, $src1", pattern
>;
class SOP2_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
opName#" $dst, $src0, $src1", pattern
>;
class SOP2_SHIFT_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
opName#" $dst, $src0, $src1", pattern
>;
class SOPC_Helper <bits<7> op, RegisterClass rc, ValueType vt,
string opName, PatLeaf cond> : SOPC <
op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
opName#" $dst, $src0, $src1", []>;
class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
: SOPC_Helper<op, SSrc_32, i32, opName, cond>;
class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
: SOPC_Helper<op, SSrc_64, i64, opName, cond>;
class SOPK_32 <bits<5> op, string opName, list<dag> pattern> : SOPK <
op, (outs SReg_32:$dst), (ins i16imm:$src0),
opName#" $dst, $src0", pattern
>;
class SOPK_64 <bits<5> op, string opName, list<dag> pattern> : SOPK <
op, (outs SReg_64:$dst), (ins i16imm:$src0),
opName#" $dst, $src0", pattern
>;
multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass baseClass,
RegisterClass dstClass> {
def _IMM : SMRD <
op, 1, (outs dstClass:$dst),
(ins baseClass:$sbase, u32imm:$offset),
asm#" $dst, $sbase, $offset", []
>;
def _SGPR : SMRD <
op, 0, (outs dstClass:$dst),
(ins baseClass:$sbase, SReg_32:$soff),
asm#" $dst, $sbase, $soff", []
>;
}
//===----------------------------------------------------------------------===//
// Vector ALU classes
//===----------------------------------------------------------------------===//
class VOP <string opName> {
string OpName = opName;
}
class VOP2_REV <string revOp, bit isOrig> {
string RevOp = revOp;
bit IsOrig = isOrig;
}
class SIMCInstr <string pseudo, int subtarget> {
string PseudoInstr = pseudo;
int Subtarget = subtarget;
}
class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
VOP3Common <outs, ins, "", pattern>,
VOP <opName>,
SIMCInstr<opName, SISubtarget.NONE> {
let isPseudo = 1;
}
class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
VOP3 <op, outs, ins, asm, []>,
SIMCInstr<opName, SISubtarget.SI>;
multiclass VOP3_m <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern,
string opName> {
def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
def _si : VOP3_Real_si <op, outs, ins, asm, opName>;
}
multiclass VOP3_1_m <bits<8> op, dag outs, dag ins, string asm,
list<dag> pattern, string opName> {
def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
let src1 = 0, src1_modifiers = 0, src2 = 0, src2_modifiers = 0 in {
def _si : VOP3_Real_si <
{1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
outs, ins, asm, opName
>;
} // src1 = 0, src1_modifiers = 0, src2 = 0, src2_modifiers = 0
}
multiclass VOP3_2_m <bits<6> op, dag outs, dag ins, string asm,
list<dag> pattern, string opName, string revOp> {
def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
let src2 = 0, src2_modifiers = 0 in {
def _si : VOP3_Real_si <
{1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
outs, ins, asm, opName>,
VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
} // src2 = 0, src2_modifiers = 0
}
// This must always be right before the operand being input modified.
def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
let PrintMethod = "printOperandAndMods";
}
multiclass VOP1_Helper <bits<8> op, RegisterClass drc, RegisterClass src,
string opName, list<dag> pattern> {
def _e32 : VOP1 <
op, (outs drc:$dst), (ins src:$src0),
opName#"_e32 $dst, $src0", pattern
>, VOP <opName>;
defm _e64 : VOP3_1_m <
op,
(outs drc:$dst),
(ins InputMods:$src0_modifiers, src:$src0, i32imm:$clamp, i32imm:$omod),
opName#"_e64 $dst, $src0_modifiers, $clamp, $omod", [], opName>;
}
multiclass VOP1_32 <bits<8> op, string opName, list<dag> pattern>
: VOP1_Helper <op, VReg_32, VSrc_32, opName, pattern>;
multiclass VOP1_64 <bits<8> op, string opName, list<dag> pattern>
: VOP1_Helper <op, VReg_64, VSrc_64, opName, pattern>;
multiclass VOP1_32_64 <bits<8> op, string opName, list<dag> pattern>
: VOP1_Helper <op, VReg_32, VSrc_64, opName, pattern>;
multiclass VOP1_64_32 <bits<8> op, string opName, list<dag> pattern>
: VOP1_Helper <op, VReg_64, VSrc_32, opName, pattern>;
multiclass VOP2_Helper <bits<6> op, RegisterClass vrc, RegisterClass arc,
string opName, list<dag> pattern, string revOp> {
def _e32 : VOP2 <
op, (outs vrc:$dst), (ins arc:$src0, vrc:$src1),
opName#"_e32 $dst, $src0, $src1", pattern
>, VOP <opName>, VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
defm _e64 : VOP3_2_m <
op,
(outs vrc:$dst),
(ins InputMods:$src0_modifiers, arc:$src0,
InputMods:$src1_modifiers, arc:$src1,
i32imm:$clamp, i32imm:$omod),
opName#"_e64 $dst, $src0_modifiers, $src1_modifiers, $clamp, $omod", [],
opName, revOp>;
}
multiclass VOP2_32 <bits<6> op, string opName, list<dag> pattern,
string revOp = opName>
: VOP2_Helper <op, VReg_32, VSrc_32, opName, pattern, revOp>;
multiclass VOP2_64 <bits<6> op, string opName, list<dag> pattern,
string revOp = opName>
: VOP2_Helper <op, VReg_64, VSrc_64, opName, pattern, revOp>;
multiclass VOP2b_32 <bits<6> op, string opName, list<dag> pattern,
RegisterClass src0_rc, string revOp = opName> {
def _e32 : VOP2 <
op, (outs VReg_32:$dst), (ins src0_rc:$src0, VReg_32:$src1),
opName#"_e32 $dst, $src0, $src1", pattern
>, VOP <opName>, VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
def _e64 : VOP3b <
{1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
(outs VReg_32:$dst),
(ins InputMods: $src0_modifiers, VSrc_32:$src0,
InputMods:$src1_modifiers, VSrc_32:$src1,
i32imm:$clamp, i32imm:$omod),
opName#"_e64 $dst, $src0_modifiers, $src1_modifiers, $clamp, $omod", []
>, VOP <opName>, VOP2_REV<revOp#"_e64", !eq(revOp, opName)> {
let src2 = 0;
let src2_modifiers = 0;
/* the VOP2 variant puts the carry out into VCC, the VOP3 variant
can write it into any SGPR. We currently don't use the carry out,
so for now hardcode it to VCC as well */
let sdst = SIOperand.VCC;
}
}
multiclass VOPC_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
string opName, ValueType vt, PatLeaf cond, bit defExec = 0> {
def _e32 : VOPC <
op, (ins arc:$src0, vrc:$src1),
opName#"_e32 $dst, $src0, $src1", []
>, VOP <opName> {
let Defs = !if(defExec, [EXEC], []);
}
def _e64 : VOP3 <
{0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
(outs SReg_64:$dst),
(ins InputMods:$src0_modifiers, arc:$src0,
InputMods:$src1_modifiers, arc:$src1,
InstFlag:$clamp, InstFlag:$omod),
opName#"_e64 $dst, $src0_modifiers, $src1_modifiers, $clamp, $omod",
!if(!eq(!cast<string>(cond), "COND_NULL"), []<dag>,
[(set SReg_64:$dst, (i1 (setcc (vt arc:$src0), arc:$src1, cond)))]
)
>, VOP <opName> {
let Defs = !if(defExec, [EXEC], []);
let src2 = 0;
let src2_modifiers = 0;
}
}
multiclass VOPC_32 <bits<8> op, string opName,
ValueType vt = untyped, PatLeaf cond = COND_NULL>
: VOPC_Helper <op, VReg_32, VSrc_32, opName, vt, cond>;
multiclass VOPC_64 <bits<8> op, string opName,
ValueType vt = untyped, PatLeaf cond = COND_NULL>
: VOPC_Helper <op, VReg_64, VSrc_64, opName, vt, cond>;
multiclass VOPCX_32 <bits<8> op, string opName,
ValueType vt = untyped, PatLeaf cond = COND_NULL>
: VOPC_Helper <op, VReg_32, VSrc_32, opName, vt, cond, 1>;
multiclass VOPCX_64 <bits<8> op, string opName,
ValueType vt = untyped, PatLeaf cond = COND_NULL>
: VOPC_Helper <op, VReg_64, VSrc_64, opName, vt, cond, 1>;
multiclass VOP3_32 <bits<9> op, string opName, list<dag> pattern> : VOP3_m <
op, (outs VReg_32:$dst),
(ins InputMods: $src0_modifiers, VSrc_32:$src0, InputMods:$src1_modifiers,
VSrc_32:$src1, InputMods:$src2_modifiers, VSrc_32:$src2,
InstFlag:$clamp, InstFlag:$omod),
opName#" $dst, $src0_modifiers, $src1, $src2, $clamp, $omod", pattern, opName
>;
class VOP3_64_32 <bits <9> op, string opName, list<dag> pattern> : VOP3 <
op, (outs VReg_64:$dst),
(ins VSrc_64:$src0, VSrc_32:$src1),
opName#" $dst, $src0, $src1", pattern
>, VOP <opName> {
let src2 = 0;
let src2_modifiers = 0;
let src0_modifiers = 0;
let clamp = 0;
let omod = 0;
}
class VOP3_64 <bits<9> op, string opName, list<dag> pattern> : VOP3 <
op, (outs VReg_64:$dst),
(ins InputMods:$src0_modifiers, VSrc_64:$src0,
InputMods:$src1_modifiers, VSrc_64:$src1,
InputMods:$src2_modifiers, VSrc_64:$src2,
InstFlag:$clamp, InstFlag:$omod),
opName#" $dst, $src0_modifiers, $src1_modifiers, $src2_modifiers, $clamp, $omod", pattern
>, VOP <opName>;
class VOP3b_Helper <bits<9> op, RegisterClass vrc, RegisterClass arc,
string opName, list<dag> pattern> : VOP3 <
op, (outs vrc:$dst0, SReg_64:$dst1),
(ins arc:$src0, arc:$src1, arc:$src2,
InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg),
opName#" $dst0, $dst1, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", pattern
>, VOP <opName>;
class VOP3b_64 <bits<9> op, string opName, list<dag> pattern> :
VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
class VOP3b_32 <bits<9> op, string opName, list<dag> pattern> :
VOP3b_Helper <op, VReg_32, VSrc_32, opName, pattern>;
//===----------------------------------------------------------------------===//
// Vector I/O classes
//===----------------------------------------------------------------------===//
class DS_1A <bits<8> op, dag outs, dag ins, string asm, list<dag> pat> :
DS <op, outs, ins, asm, pat> {
bits<16> offset;
// Single load interpret the 2 i8imm operands as a single i16 offset.
let offset0 = offset{7-0};
let offset1 = offset{15-8};
}
class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
op,
(outs regClass:$vdst),
(ins i1imm:$gds, VReg_32:$addr, u16imm:$offset),
asm#" $vdst, $addr, $offset, [M0]",
[]> {
let data0 = 0;
let data1 = 0;
let mayLoad = 1;
let mayStore = 0;
}
class DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
op,
(outs regClass:$vdst),
(ins i1imm:$gds, VReg_32:$addr, u8imm:$offset0, u8imm:$offset1),
asm#" $gds, $vdst, $addr, $offset0, $offset1, [M0]",
[]> {
let data0 = 0;
let data1 = 0;
let mayLoad = 1;
let mayStore = 0;
}
class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
op,
(outs),
(ins i1imm:$gds, VReg_32:$addr, regClass:$data0, u16imm:$offset),
asm#" $addr, $data0, $offset [M0]",
[]> {
let data1 = 0;
let mayStore = 1;
let mayLoad = 0;
let vdst = 0;
}
class DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
op,
(outs),
(ins i1imm:$gds, VReg_32:$addr, regClass:$data0, u8imm:$offset0, u8imm:$offset1),
asm#" $addr, $data0, $data1, $offset0, $offset1 [M0]",
[]> {
let mayStore = 1;
let mayLoad = 0;
let vdst = 0;
}
// 1 address, 1 data.
class DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc> : DS_1A <
op,
(outs rc:$vdst),
(ins i1imm:$gds, VReg_32:$addr, rc:$data0, u16imm:$offset),
asm#" $vdst, $addr, $data0, $offset, [M0]",
[]> {
let data1 = 0;
let mayStore = 1;
let mayLoad = 1;
}
// 1 address, 2 data.
class DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc> : DS_1A <
op,
(outs rc:$vdst),
(ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, u16imm:$offset),
asm#" $vdst, $addr, $data0, $data1, $offset, [M0]",
[]> {
let mayStore = 1;
let mayLoad = 1;
}
// 1 address, 2 data.
class DS_1A2D_NORET <bits<8> op, string asm, RegisterClass rc> : DS_1A <
op,
(outs),
(ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, u16imm:$offset),
asm#" $addr, $data0, $data1, $offset, [M0]",
[]> {
let mayStore = 1;
let mayLoad = 1;
}
// 1 address, 1 data.
class DS_1A1D_NORET <bits<8> op, string asm, RegisterClass rc> : DS_1A <
op,
(outs),
(ins i1imm:$gds, VReg_32:$addr, rc:$data0, u16imm:$offset),
asm#" $addr, $data0, $offset, [M0]",
[]> {
let data1 = 0;
let mayStore = 1;
let mayLoad = 1;
}
class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
op,
(outs),
(ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
asm#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
#" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset",
[]> {
let mayStore = 1;
let mayLoad = 0;
}
multiclass MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass,
ValueType load_vt = i32,
SDPatternOperator ld = null_frag> {
let lds = 0, mayLoad = 1 in {
let addr64 = 0 in {
let offen = 0, idxen = 0, vaddr = 0 in {
def _OFFSET : MUBUF <op, (outs regClass:$vdata),
(ins SReg_128:$srsrc,
u16imm:$offset, SSrc_32:$soffset, i1imm:$glc,
i1imm:$slc, i1imm:$tfe),
asm#" $vdata, $srsrc + $offset + $soffset, glc=$glc, slc=$slc, tfe=$tfe", []>;
}
let offen = 1, idxen = 0 in {
def _OFFEN : MUBUF <op, (outs regClass:$vdata),
(ins SReg_128:$srsrc, VReg_32:$vaddr,
SSrc_32:$soffset, u16imm:$offset, i1imm:$glc, i1imm:$slc,
i1imm:$tfe),
asm#" $vdata, $srsrc + $vaddr + $soffset + $offset, glc=$glc, slc=$slc, tfe=$tfe", []>;
}
let offen = 0, idxen = 1 in {
def _IDXEN : MUBUF <op, (outs regClass:$vdata),
(ins SReg_128:$srsrc, VReg_32:$vaddr,
u16imm:$offset, SSrc_32:$soffset, i1imm:$glc,
i1imm:$slc, i1imm:$tfe),
asm#" $vdata, $srsrc[$vaddr] + $offset + $soffset, glc=$glc, slc=$slc, tfe=$tfe", []>;
}
let offen = 1, idxen = 1 in {
def _BOTHEN : MUBUF <op, (outs regClass:$vdata),
(ins SReg_128:$srsrc, VReg_64:$vaddr,
SSrc_32:$soffset, i1imm:$glc,
i1imm:$slc, i1imm:$tfe),
asm#" $vdata, $srsrc[$vaddr[0]] + $vaddr[1] + $soffset, glc=$glc, slc=$slc, tfe=$tfe", []>;
}
}
let offen = 0, idxen = 0, addr64 = 1, glc = 0, slc = 0, tfe = 0, soffset = 128 /* ZERO */ in {
def _ADDR64 : MUBUF <op, (outs regClass:$vdata),
(ins SReg_128:$srsrc, VReg_64:$vaddr, u16imm:$offset),
asm#" $vdata, $srsrc + $vaddr + $offset",
[(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
i64:$vaddr, u16imm:$offset)))]>;
}
}
}
multiclass MUBUF_Store_Helper <bits<7> op, string name, RegisterClass vdataClass,
ValueType store_vt, SDPatternOperator st> {
def "" : MUBUF <
op, (outs),
(ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SSrc_32:$soffset,
u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$slc,
i1imm:$tfe),
name#" $vdata, $srsrc, $vaddr, $soffset, $offset $offen $idxen $glc $slc $tfe",
[]
> {
let addr64 = 0;
}
def _ADDR64 : MUBUF <
op, (outs),
(ins vdataClass:$vdata, SReg_128:$srsrc, VReg_64:$vaddr, u16imm:$offset),
name#" $vdata, $srsrc + $vaddr + $offset",
[(st store_vt:$vdata,
(MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, u16imm:$offset))]> {
let mayLoad = 0;
let mayStore = 1;
// Encoding
let offen = 0;
let idxen = 0;
let glc = 0;
let addr64 = 1;
let lds = 0;
let slc = 0;
let tfe = 0;
let soffset = 128; // ZERO
}
}
class MTBUF_Load_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
op,
(outs regClass:$dst),
(ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, SReg_128:$srsrc,
i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
asm#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
#" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset",
[]> {
let mayLoad = 1;
let mayStore = 0;
}
class MIMG_Mask <string op, int channels> {
string Op = op;
int Channels = channels;
}
class MIMG_NoSampler_Helper <bits<7> op, string asm,
RegisterClass dst_rc,
RegisterClass src_rc> : MIMG <
op,
(outs dst_rc:$vdata),
(ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
SReg_256:$srsrc),
asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
#" $tfe, $lwe, $slc, $vaddr, $srsrc",
[]> {
let SSAMP = 0;
let mayLoad = 1;
let mayStore = 0;
let hasPostISelHook = 1;
}
multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
RegisterClass dst_rc,
int channels> {
def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_32>,
MIMG_Mask<asm#"_V1", channels>;
def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
MIMG_Mask<asm#"_V2", channels>;
def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
MIMG_Mask<asm#"_V4", channels>;
}
multiclass MIMG_NoSampler <bits<7> op, string asm> {
defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VReg_32, 1>;
defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
}
class MIMG_Sampler_Helper <bits<7> op, string asm,
RegisterClass dst_rc,
RegisterClass src_rc> : MIMG <
op,
(outs dst_rc:$vdata),
(ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
SReg_256:$srsrc, SReg_128:$ssamp),
asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
#" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
[]> {
let mayLoad = 1;
let mayStore = 0;
let hasPostISelHook = 1;
}
multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
RegisterClass dst_rc,
int channels> {
def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_32>,
MIMG_Mask<asm#"_V1", channels>;
def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64>,
MIMG_Mask<asm#"_V2", channels>;
def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128>,
MIMG_Mask<asm#"_V4", channels>;
def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256>,
MIMG_Mask<asm#"_V8", channels>;
def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512>,
MIMG_Mask<asm#"_V16", channels>;
}
multiclass MIMG_Sampler <bits<7> op, string asm> {
defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VReg_32, 1>;
defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2>;
defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3>;
defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4>;
}
class MIMG_Gather_Helper <bits<7> op, string asm,
RegisterClass dst_rc,
RegisterClass src_rc> : MIMG <
op,
(outs dst_rc:$vdata),
(ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
SReg_256:$srsrc, SReg_128:$ssamp),
asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
#" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
[]> {
let mayLoad = 1;
let mayStore = 0;
// DMASK was repurposed for GATHER4. 4 components are always
// returned and DMASK works like a swizzle - it selects
// the component to fetch. The only useful DMASK values are
// 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
// (red,red,red,red) etc.) The ISA document doesn't mention
// this.
// Therefore, disable all code which updates DMASK by setting these two:
let MIMG = 0;
let hasPostISelHook = 0;
}
multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
RegisterClass dst_rc,
int channels> {
def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_32>,
MIMG_Mask<asm#"_V1", channels>;
def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64>,
MIMG_Mask<asm#"_V2", channels>;
def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128>,
MIMG_Mask<asm#"_V4", channels>;
def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256>,
MIMG_Mask<asm#"_V8", channels>;
def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512>,
MIMG_Mask<asm#"_V16", channels>;
}
multiclass MIMG_Gather <bits<7> op, string asm> {
defm _V1 : MIMG_Gather_Src_Helper<op, asm, VReg_32, 1>;
defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2>;
defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3>;
defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4>;
}
//===----------------------------------------------------------------------===//
// Vector instruction mappings
//===----------------------------------------------------------------------===//
// Maps an opcode in e32 form to its e64 equivalent
def getVOPe64 : InstrMapping {
let FilterClass = "VOP";
let RowFields = ["OpName"];
let ColFields = ["Size"];
let KeyCol = ["4"];
let ValueCols = [["8"]];
}
// Maps an opcode in e64 form to its e32 equivalent
def getVOPe32 : InstrMapping {
let FilterClass = "VOP";
let RowFields = ["OpName"];
let ColFields = ["Size"];
let KeyCol = ["8"];
let ValueCols = [["4"]];
}
// Maps an original opcode to its commuted version
def getCommuteRev : InstrMapping {
let FilterClass = "VOP2_REV";
let RowFields = ["RevOp"];
let ColFields = ["IsOrig"];
let KeyCol = ["1"];
let ValueCols = [["0"]];
}
def getMaskedMIMGOp : InstrMapping {
let FilterClass = "MIMG_Mask";
let RowFields = ["Op"];
let ColFields = ["Channels"];
let KeyCol = ["4"];
let ValueCols = [["1"], ["2"], ["3"] ];
}
// Maps an commuted opcode to its original version
def getCommuteOrig : InstrMapping {
let FilterClass = "VOP2_REV";
let RowFields = ["RevOp"];
let ColFields = ["IsOrig"];
let KeyCol = ["0"];
let ValueCols = [["1"]];
}
def isDS : InstrMapping {
let FilterClass = "DS";
let RowFields = ["Inst"];
let ColFields = ["Size"];
let KeyCol = ["8"];
let ValueCols = [["8"]];
}
def getMCOpcode : InstrMapping {
let FilterClass = "SIMCInstr";
let RowFields = ["PseudoInstr"];
let ColFields = ["Subtarget"];
let KeyCol = [!cast<string>(SISubtarget.NONE)];
let ValueCols = [[!cast<string>(SISubtarget.SI)]];
}
include "SIInstructions.td"
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