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Summary: constrainOperandRegClass() currently fails if it tries to constrain the register class of an operand that is defeined with an unallocatable register class. This patch resolves this by adding a target callback to compute register constriants in this case. This is required by the AMDGPU because many of its instructions have source opreands defined with the unallocatable register classe VS_32 which is a union of two allocatable register classes VGPR_32 and SReg_32. Reviewers: dsanders, aditya_nandakumar Reviewed By: aditya_nandakumar Subscribers: rovka, kristof.beyls, tpr, llvm-commits Differential Revision: https://reviews.llvm.org/D45991 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331485 91177308-0d34-0410-b5e6-96231b3b80d8
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