Sam Parker 580eedab52 [ARM] DLS/LE low-overhead loop code generation ...

Introduce three pseudo instructions to be used during DAG ISel to
represent v8.1-m low-overhead loops. One maps to set_loop_iterations
while loop_decrement_reg is lowered to two, so that we can separate
the decrement and branching operations. The pseudo instructions are
expanded pre-emission, where we can still decide whether we actually
want to generate a low-overhead loop, in a new pass:
ARMLowOverheadLoops. The pass currently bails, reverting to an sub,
icmp and br, in the cases where a call or stack spill/restore happens
between the decrement and branching instructions, or if the loop is
too large.

Differential Revision: https://reviews.llvm.org/D63476


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364288 91177308-0d34-0410-b5e6-96231b3b80d8

2019-06-25 10:45:51 +00:00

..

ARM

[ARM] DLS/LE low-overhead loop code generation

2019-06-25 10:45:51 +00:00

scalar-while.ll

[CodeGen] Generic Hardware Loop Support

2019-06-07 07:35:30 +00:00

unconditional-latch.ll

[CodeGen] Check for HardwareLoop Latch ExitBlock

2019-06-17 13:39:28 +00:00

unscevable.ll

[CodeGen] Generic Hardware Loop Support

2019-06-07 07:35:30 +00:00